2 * (C) Copyright 2013 Keymile AG
3 * Valentin Longchamp <valentin.longchamp@keymile.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _CONFIG_KMP204X_H
9 #define _CONFIG_KMP204X_H
11 #define CONFIG_SYS_TEXT_BASE 0xfff40000
13 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
15 /* an additionnal option is required for UBI as subpage access is
16 * supported in u-boot */
17 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
19 #define CONFIG_NAND_ECC_BCH
21 /* common KM defines */
22 #include "keymile-common.h"
24 #define CONFIG_SYS_RAMBOOT
25 #define CONFIG_RAMBOOT_PBL
26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
28 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
29 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
31 /* High Level Configuration Options */
32 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
33 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
34 #define CONFIG_MP /* support multiple processors */
36 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
37 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
38 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
39 #define CONFIG_PCIE1 /* PCIE controller 1 */
40 #define CONFIG_PCIE3 /* PCIE controller 3 */
41 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
42 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
44 #define CONFIG_SYS_DPAA_RMAN /* RMan */
46 /* Environment in SPI Flash */
47 #define CONFIG_SYS_EXTRA_ENV_RELOC
48 #define CONFIG_ENV_IS_IN_SPI_FLASH
49 #define CONFIG_ENV_SPI_BUS 0
50 #define CONFIG_ENV_SPI_CS 0
51 #define CONFIG_ENV_SPI_MAX_HZ 20000000
52 #define CONFIG_ENV_SPI_MODE 0
53 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */
54 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */
55 #define CONFIG_ENV_SECT_SIZE 0x010000
56 #define CONFIG_ENV_OFFSET_REDUND 0x110000
57 #define CONFIG_ENV_TOTAL_SIZE 0x020000
59 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
62 unsigned long get_board_sys_clk(unsigned long dummy);
64 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
67 * These can be toggled for performance analysis, otherwise use default.
69 #define CONFIG_SYS_CACHE_STASHING
70 #define CONFIG_BACKSIDE_L2_CACHE
71 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
72 #define CONFIG_BTB /* toggle branch predition */
74 #define CONFIG_ENABLE_36BIT_PHYS
76 #define CONFIG_ADDR_MAP
77 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
79 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
82 * Config the L3 Cache as L3 SRAM
84 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
85 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
86 CONFIG_RAMBOOT_TEXT_BASE)
87 #define CONFIG_SYS_L3_SIZE (1024 << 10)
88 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
90 #define CONFIG_SYS_DCSRBAR 0xf0000000
91 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
96 #define CONFIG_VERY_BIG_RAM
97 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
98 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
100 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
101 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
103 #define CONFIG_DDR_SPD
104 #define CONFIG_SYS_FSL_DDR3
105 #define CONFIG_FSL_DDR_INTERACTIVE
107 #define CONFIG_SYS_SPD_BUS_NUM 0
108 #define SPD_EEPROM_ADDRESS 0x54
109 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
111 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
112 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
114 /******************************************************************************
116 * ... -------------------------------------------------------
117 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
118 * ... |<------------------- pram -------------------------->|
119 * ... -------------------------------------------------------
121 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
122 * @CONFIG_KM_PHRAM: address for /var
123 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
124 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
127 /* size of rootfs in RAM */
128 #define CONFIG_KM_ROOTFSSIZE 0x0
129 /* pseudo-non volatile RAM [hex] */
130 #define CONFIG_KM_PNVRAM 0x80000
131 /* physical RAM MTD size [hex] */
132 #define CONFIG_KM_PHRAM 0x100000
133 /* reserved pram area at the end of memory [hex]
134 * u-boot reserves some memory for the MP boot page */
135 #define CONFIG_KM_RESERVED_PRAM 0x1000
136 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
137 * is not valid yet, which is the case for when u-boot copies itself to RAM */
138 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
140 #define CONFIG_KM_CRAMFS_ADDR 0x2000000
141 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
142 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */
145 * Local Bus Definitions
148 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
149 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2)
152 #define CONFIG_NAND_FSL_ELBC
153 #define CONFIG_SYS_NAND_BASE 0xffa00000
154 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
156 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
157 #define CONFIG_SYS_MAX_NAND_DEVICE 1
158 #define CONFIG_CMD_NAND
159 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
163 /* NAND flash config */
164 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
165 | BR_PS_8 /* Port Size = 8 bit */ \
166 | BR_MS_FCM /* MSEL = FCM */ \
169 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
170 | OR_FCM_BCTLD /* LBCTL not ass */ \
171 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \
172 | OR_FCM_RST /* 1 clk read setup */ \
173 | OR_FCM_PGS /* Large page size */ \
174 | OR_FCM_CST) /* 0.25 command setup */
176 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
177 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
180 #define CONFIG_SYS_QRIO_BASE 0xfb000000
181 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
183 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
184 | BR_PS_8 /* Port Size 8 bits */ \
185 | BR_DECC_OFF /* no error corr */ \
186 | BR_MS_GPCM /* MSEL = GPCM */ \
189 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \
190 | OR_GPCM_BCTLD /* no LCTL assert */ \
191 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
192 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
193 | OR_GPCM_TRLX /* relaxed tmgs */ \
194 | OR_GPCM_EAD) /* extra bus clk cycles */
196 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
197 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
199 /* bootcounter in QRIO */
200 #define CONFIG_BOOTCOUNT_LIMIT
201 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20)
203 #define CONFIG_BOARD_EARLY_INIT_F
204 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
205 #define CONFIG_MISC_INIT_F
206 #define CONFIG_MISC_INIT_R
207 #define CONFIG_LAST_STAGE_INIT
209 #define CONFIG_HWCONFIG
211 /* define to use L1 as initial stack */
212 #define CONFIG_L1_INIT_RAM
213 #define CONFIG_SYS_INIT_RAM_LOCK
214 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
215 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
216 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
217 /* The assembler doesn't like typecast */
218 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
219 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
220 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
221 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
223 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
224 GENERATED_GBL_DATA_SIZE)
225 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
227 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
228 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
229 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
231 /* Serial Port - controlled on board with jumper J8
235 #define CONFIG_CONS_INDEX 1
236 #define CONFIG_SYS_NS16550_SERIAL
237 #define CONFIG_SYS_NS16550_REG_SIZE 1
238 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
240 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
241 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
242 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
243 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
245 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
249 #define CONFIG_SYS_I2C
250 #define CONFIG_SYS_I2C_INIT_BOARD
251 #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */
252 #define CONFIG_SYS_NUM_I2C_BUSES 3
253 #define CONFIG_SYS_I2C_MAX_HOPS 1
254 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */
255 #define CONFIG_I2C_MULTI_BUS
256 #define CONFIG_I2C_CMD_TREE
257 #define CONFIG_SYS_FSL_I2C_SPEED 400000
258 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
259 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
260 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
261 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
262 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
265 void set_sda(int state);
266 void set_scl(int state);
271 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
274 * eSPI - Enhanced SPI
276 #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */
277 #define CONFIG_SF_DEFAULT_SPEED 20000000
278 #define CONFIG_SF_DEFAULT_MODE 0
282 * Memory space is mapped 1-1, but I/O space must start from 0.
285 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
286 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
287 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
288 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
289 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
290 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
291 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
292 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
293 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
295 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
296 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
297 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
298 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
299 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
300 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
301 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
302 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
303 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
306 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
307 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
308 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
309 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
310 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
311 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
312 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
313 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
314 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
315 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
316 CONFIG_SYS_BMAN_CENA_SIZE)
317 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
318 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
319 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
320 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
321 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
322 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
323 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
324 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
325 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
326 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
327 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
328 CONFIG_SYS_QMAN_CENA_SIZE)
329 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
330 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
332 #define CONFIG_SYS_DPAA_FMAN
333 #define CONFIG_SYS_DPAA_PME
334 /* Default address of microcode for the Linux Fman driver
335 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
336 * ucode is stored after env, so we got 0x120000.
338 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
339 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000
340 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
341 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
343 #define CONFIG_FMAN_ENET
344 #define CONFIG_PHYLIB_10G
345 #define CONFIG_PHY_MARVELL /* there is a marvell phy */
347 #define CONFIG_PCI_INDIRECT_BRIDGE
349 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
350 #define CONFIG_DOS_PARTITION
352 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
353 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
354 #define CONFIG_SYS_TBIPA_VALUE 8
355 #define CONFIG_PHYLIB /* recommended PHY management */
356 #define CONFIG_ETHPRIME "FM1@DTSEC5"
357 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
362 #define CONFIG_LOADS_ECHO /* echo on for serial download */
363 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
368 #define CONFIG_WATCHDOG /* enable CPU watchdog */
369 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */
370 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
374 * additionnal command line configuration.
376 #define CONFIG_CMD_PCI
377 #define CONFIG_CMD_ERRATA
379 /* we don't need flash support */
380 #define CONFIG_SYS_NO_FLASH
381 #undef CONFIG_FLASH_CFI_MTD
382 #undef CONFIG_JFFS2_CMDLINE
385 * For booting Linux, the board info and command line data
386 * have to be in the first 64 MB of memory, since this is
387 * the maximum mapped by the Linux kernel during initialization.
389 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
390 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
392 #ifdef CONFIG_CMD_KGDB
393 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
396 #define __USB_PHY_TYPE utmi
397 #define CONFIG_USB_EHCI_FSL
400 * Environment Configuration
402 #define CONFIG_ENV_OVERWRITE
403 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
404 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
407 #ifndef MTDIDS_DEFAULT
408 # define MTDIDS_DEFAULT "nand0=fsl_elbc_nand"
409 #endif /* MTDIDS_DEFAULT */
411 #ifndef MTDPARTS_DEFAULT
412 # define MTDPARTS_DEFAULT "mtdparts=" \
414 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
415 #endif /* MTDPARTS_DEFAULT */
417 /* architecture specific default bootargs */
418 #define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
420 /* FIXME: FDT_ADDR is unspecified */
421 #define CONFIG_KM_DEF_ENV_CPU \
422 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
424 "cramfsload ${fdt_addr_r} " \
425 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
426 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
427 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \
429 "sf probe 0;sf erase 0 +${filesize};" \
430 "sf write ${load_addr_r} 0 ${filesize};\0" \
431 "set_fdthigh=true\0" \
435 #define CONFIG_HW_ENV_SETTINGS \
436 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
437 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
440 #define CONFIG_KM_NEW_ENV \
441 "newenv=sf probe 0;" \
442 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
443 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
445 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
446 #ifndef CONFIG_KM_DEF_ARCH
447 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
450 #define CONFIG_EXTRA_ENV_SETTINGS \
454 CONFIG_HW_ENV_SETTINGS \
455 "EEprom_ivm=pca9547:70:9\0" \
458 #endif /* _CONFIG_KMP204X_H */