2 * (C) Copyright 2007-2011
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC8247
34 #if defined(CONFIG_MGCOGE)
35 #define CONFIG_HOSTNAME mgcoge
36 #define CONFIG_KM_BOARD_EXTRA_ENV ""
39 #elif defined(CONFIG_MGCOGE3NE)
40 #define CONFIG_HOSTNAME mgcoge3ne
41 #define CONFIG_KM_82XX
42 #define CONFIG_KM_BOARD_EXTRA_ENV "bobcatreset=true\0"
45 #error ("Board unsupported")
48 #define CONFIG_SYS_TEXT_BASE 0xFE000000
50 /* include common defines/options for all Keymile boards */
51 #include "km/keymile-common.h"
52 #include "km/km-powerpc.h"
54 #define CONFIG_SYS_SDRAM_BASE 0x00000000
55 #define CONFIG_SYS_FLASH_BASE 0xFE000000
56 #define CONFIG_SYS_FLASH_SIZE 32
57 #define CONFIG_SYS_FLASH_CFI
58 #define CONFIG_FLASH_CFI_DRIVER
61 #if defined(CONFIG_MGCOGE)
62 #define CONFIG_SYS_MAX_FLASH_BANKS 3
63 /* max num of sects on one chip */
64 #define CONFIG_SYS_MAX_FLASH_SECT 512
66 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
67 #define CONFIG_SYS_FLASH_SIZE_1 32
68 #define CONFIG_SYS_FLASH_BASE_2 0x52000000
69 #define CONFIG_SYS_FLASH_SIZE_2 32
71 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
72 CONFIG_SYS_FLASH_BASE_1, \
73 CONFIG_SYS_FLASH_BASE_2 }
74 #define MTDIDS_DEFAULT "nor3=app"
77 * Bank 1 - 60x bus SDRAM
79 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
80 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
82 /* SDRAM initialization values
85 #define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
91 #define CONFIG_SYS_PSDMR ( \
92 PSDMR_SDAM_A14_IS_A5 |\
94 PSDMR_SDA10_PBI0_A9 |\
103 #elif defined(CONFIG_MGCOGE3NE)
104 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
105 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /*
106 * max num of sects on one
110 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
111 #define CONFIG_SYS_FLASH_SIZE_1 128
113 #define CONFIG_SYS_FLASH_SIZE_2 0 /* dummy value to calc SYS_OR5 */
115 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
116 CONFIG_SYS_FLASH_BASE_1 }
118 #define MTDIDS_DEFAULT "nor2=app"
121 * Bank 1 - 60x bus SDRAM
122 * mgcoge3ne has 256M.
124 #define SDRAM_MAX_SIZE 0x10000000 /* max. 256 MB */
125 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512 << 20) /* less than 512 MB */
127 #define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
130 ORxS_ROWST_PBI1_A4 |\
133 #define CONFIG_SYS_PSDMR ( \
135 PSDMR_SDAM_A17_IS_A5 |\
136 PSDMR_BSMA_A13_A15 |\
137 PSDMR_SDA10_PBI1_A6 |\
144 #endif /* defined(CONFIG_MGCOGE3NE) */
146 /* include further common stuff for all keymile 82xx boards */
148 * Select serial console configuration
150 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
151 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
154 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
155 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
156 #undef CONFIG_CONS_NONE /* It's not on external UART */
157 #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
158 #define CONFIG_SYS_SMC_RXBUFLEN 128
159 #define CONFIG_SYS_MAXIDLE 10
162 * Select ethernet configuration
164 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
165 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
168 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
169 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
172 #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
173 #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
174 #undef CONFIG_ETHER_NONE /* No external Ethernet */
176 #define CONFIG_ETHER_INDEX 4
177 #define CONFIG_HAS_ETH0
178 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000
180 #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
182 #ifndef CONFIG_8260_CLKIN
183 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
186 #define BOOTFLASH_START 0xFE000000
188 #define CONFIG_KM_CONSOLE_TTY "ttyCPM0"
190 #define MTDPARTS_DEFAULT "mtdparts=" \
196 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")"
199 * Default environment settings
201 #define CONFIG_EXTRA_ENV_SETTINGS \
202 CONFIG_KM_BOARD_EXTRA_ENV \
204 "EEprom_ivm=pca9544a:70:4 \0" \
207 "prot off 0xFE0C0000 +0x40000 && " \
208 "era 0xFE0C0000 +0x40000\0" \
212 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
213 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
214 #define CONFIG_SYS_RAMBOOT
217 #define CONFIG_SYS_MONITOR_LEN (768 << 10)
219 #define CONFIG_ENV_IS_IN_FLASH
221 #ifdef CONFIG_ENV_IS_IN_FLASH
222 #define CONFIG_ENV_SECT_SIZE 0x20000
223 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
224 CONFIG_SYS_MONITOR_LEN)
225 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
227 /* Address and size of Redundant Environment Sector */
228 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
229 CONFIG_ENV_SECT_SIZE)
230 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
231 #endif /* CONFIG_ENV_IS_IN_FLASH */
233 /* enable I2C and select the hardware/software driver */
234 #undef CONFIG_HARD_I2C /* I2C with hardware support */
235 #define CONFIG_SOFT_I2C /* I2C bit-banged */
236 #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed */
237 #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
240 * Software (bit-bang) I2C driver configuration
243 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
244 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
245 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
246 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
247 #define I2C_SDA(bit) do { \
249 iop->pdat |= 0x00010000; \
251 iop->pdat &= ~0x00010000; \
253 #define I2C_SCL(bit) do { \
255 iop->pdat |= 0x00020000; \
257 iop->pdat &= ~0x00020000; \
259 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
262 void set_sda(int state);
263 void set_scl(int state);
268 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
269 #define CONFIG_DTT_LM75 /* ON Semi's LM75 */
270 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
271 #define CONFIG_SYS_DTT_MAX_TEMP 70
272 #define CONFIG_SYS_DTT_LOW_TEMP -30
273 #define CONFIG_SYS_DTT_HYSTERESIS 3
274 #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
276 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
278 #define CONFIG_SYS_IMMR 0xF0000000
280 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
281 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */
282 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
283 GENERATED_GBL_DATA_SIZE)
284 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
286 /* Hard reset configuration word */
287 #define CONFIG_SYS_HRCW_MASTER 0x0604b211
290 #define CONFIG_SYS_HRCW_SLAVE1 0
291 #define CONFIG_SYS_HRCW_SLAVE2 0
292 #define CONFIG_SYS_HRCW_SLAVE3 0
293 #define CONFIG_SYS_HRCW_SLAVE4 0
294 #define CONFIG_SYS_HRCW_SLAVE5 0
295 #define CONFIG_SYS_HRCW_SLAVE6 0
296 #define CONFIG_SYS_HRCW_SLAVE7 0
298 /* Initial Memory map for Linux */
299 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
301 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
302 #if defined(CONFIG_CMD_KGDB)
303 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
306 #define CONFIG_SYS_HID0_INIT 0
307 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
309 #define CONFIG_SYS_HID2 0
311 #define CONFIG_SYS_SIUMCR 0x4020c200
312 #define CONFIG_SYS_SYPCR 0xFFFFFF83
313 #define CONFIG_SYS_BCR 0x10000000
314 #define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
317 *-----------------------------------------------------------------------
318 * RMR - Reset Mode Register 5-5
319 *-----------------------------------------------------------------------
320 * turn on Checkstop Reset Enable
322 #define CONFIG_SYS_RMR 0
325 *-----------------------------------------------------------------------
326 * TMCNTSC - Time Counter Status and Control 4-40
327 *-----------------------------------------------------------------------
328 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
329 * and enable Time Counter
331 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
334 *-----------------------------------------------------------------------
335 * PISCR - Periodic Interrupt Status and Control 4-42
336 *-----------------------------------------------------------------------
337 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
340 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
343 *-----------------------------------------------------------------------
344 * RCCR - RISC Controller Configuration 13-7
345 *-----------------------------------------------------------------------
347 #define CONFIG_SYS_RCCR 0
350 * Init Memory Controller:
352 * Bank Bus Machine PortSz Device
353 * ---- --- ------- ------ ------
354 * 0 60x GPCM 8 bit FLASH
355 * 1 60x SDRAM 32 bit SDRAM
356 * 3 60x GPCM 8 bit GPIO/PIGGY
357 * 5 60x GPCM 16 bit CFG-Flash
362 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
367 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
373 #define CONFIG_SYS_MPTPR 0x1800
376 *-----------------------------------------------------------------------------
377 * Address for Mode Register Set (MRS) command
378 *-----------------------------------------------------------------------------
380 #define CONFIG_SYS_MRS_OFFS 0x00000110
381 #define CONFIG_SYS_PSRT 0x0e
383 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
388 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
391 * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
393 #define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000
394 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
396 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
397 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
399 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
400 ORxG_CSNT | ORxG_ACS_DIV2 |\
401 ORxG_SCY_3_CLK | ORxG_TRLX)
404 * BFTICU board FPGA on CS4 initialization values
406 #define CONFIG_SYS_FPGA_BASE 0x40000000
407 #define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
409 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
410 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
412 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
413 ORxG_CSNT | ORxG_ACS_DIV2 |\
414 ORxG_SCY_3_CLK | ORxG_TRLX)
417 * CFG-Flash on CS5 initialization values
419 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
420 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
422 #define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
423 CONFIG_SYS_FLASH_SIZE_2) |\
424 ORxG_CSNT | ORxG_ACS_DIV2 |\
425 ORxG_SCY_5_CLK | ORxG_TRLX)
427 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
429 /* pass open firmware flat tree */
431 #define CONFIG_OF_LIBFDT 1
432 #define CONFIG_OF_BOARD_SETUP 1
434 #define OF_TBCLK (bd->bi_busfreq / 4)
435 #define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
437 #endif /* __CONFIG_H */