2 * include/configs/lager.h
3 * This file is lager board configuration.
5 * Copyright (C) 2013 Renesas Electronics Corporation
7 * SPDX-License-Identifier: GPL-2.0
15 #define CONFIG_R8A7790
16 #define CONFIG_RMOBILE
17 #define CONFIG_RMOBILE_BOARD_STRING "Lager"
18 #define CONFIG_SH_GPIO_PFC
20 #include <asm/arch/rmobile.h>
22 #define CONFIG_CMD_EDITENV
23 #define CONFIG_CMD_SAVEENV
24 #define CONFIG_CMD_MEMORY
25 #define CONFIG_CMD_DFL
26 #define CONFIG_CMD_SDRAM
27 #define CONFIG_CMD_RUN
28 #define CONFIG_CMD_LOADS
29 #define CONFIG_CMD_NET
30 #define CONFIG_CMD_MII
31 #define CONFIG_CMD_PING
32 #define CONFIG_CMD_DHCP
33 #define CONFIG_CMD_NFS
34 #define CONFIG_CMD_BOOTZ
37 #define CONFIG_CMD_SPI
38 #define CONFIG_SYS_TEXT_BASE 0xE8080000
39 #define CONFIG_SYS_THUMB_BUILD
41 #define CONFIG_CMDLINE_TAG
42 #define CONFIG_SETUP_MEMORY_TAGS
43 #define CONFIG_INITRD_TAG
44 #define CONFIG_CMDLINE_EDITING
45 #define CONFIG_OF_LIBFDT
47 /* #define CONFIG_OF_LIBFDT */
48 #define BOARD_LATE_INIT
50 #define CONFIG_BAUDRATE 38400
51 #define CONFIG_BOOTDELAY 3
52 #define CONFIG_BOOTARGS ""
54 #define CONFIG_VERSION_VARIABLE
55 #undef CONFIG_SHOW_BOOT_PROGRESS
57 #define CONFIG_ARCH_CPU_INIT
58 #define CONFIG_DISPLAY_CPUINFO
59 #define CONFIG_DISPLAY_BOARDINFO
60 #define CONFIG_BOARD_EARLY_INIT_F
61 #define CONFIG_TMU_TIMER
64 #define CONFIG_SYS_INIT_SP_ADDR 0xE827fffc
65 #define STACK_AREA_SIZE 0xC000
66 #define LOW_LEVEL_MERAM_STACK \
67 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
70 #define LAGER_SDRAM_BASE 0x40000000
71 #define LAGER_SDRAM_SIZE (2048u * 1024 * 1024)
72 #define LAGER_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
74 #define CONFIG_SYS_LONGHELP
75 #define CONFIG_SYS_CBSIZE 256
76 #define CONFIG_SYS_PBSIZE 256
77 #define CONFIG_SYS_MAXARGS 16
78 #define CONFIG_SYS_BARGSIZE 512
79 #define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
82 #define CONFIG_SCIF_CONSOLE
83 #define CONFIG_CONS_SCIF0
84 #undef CONFIG_SYS_CONSOLE_INFO_QUIET
85 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
86 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
88 #define CONFIG_SYS_MEMTEST_START (LAGER_SDRAM_BASE)
89 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
91 #undef CONFIG_SYS_ALT_MEMTEST
92 #undef CONFIG_SYS_MEMTEST_SCRATCH
93 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
95 #define CONFIG_SYS_SDRAM_BASE (LAGER_SDRAM_BASE)
96 #define CONFIG_SYS_SDRAM_SIZE (LAGER_UBOOT_SDRAM_SIZE)
97 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0)
98 #define CONFIG_NR_DRAM_BANKS 1
100 #define CONFIG_SYS_MONITOR_BASE 0x00000000
101 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
102 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
103 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
107 #define CONFIG_SPI_FLASH_BAR
108 #define CONFIG_SH_QSPI
109 #define CONFIG_SPI_FLASH
110 #define CONFIG_SPI_FLASH_SPANSION
111 #define CONFIG_SYS_NO_FLASH
114 #define CONFIG_ENV_IS_IN_SPI_FLASH
115 #define CONFIG_ENV_ADDR 0xC0000
117 /* Common ENV setting */
118 #define CONFIG_ENV_OVERWRITE
119 #define CONFIG_ENV_SECT_SIZE (256 * 1024)
120 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
121 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
122 #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
125 #define CONFIG_NET_MULTI
126 #define CONFIG_SH_ETHER
127 #define CONFIG_SH_ETHER_USE_PORT 0
128 #define CONFIG_SH_ETHER_PHY_ADDR 0x1
129 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
130 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64
131 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
132 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
133 #define CONFIG_PHYLIB
134 #define CONFIG_PHY_MICREL
135 #define CONFIG_BITBANGMII
136 #define CONFIG_BITBANGMII_MULTI
139 #define CONFIG_SYS_I2C
140 #define CONFIG_SYS_I2C_RCAR
141 #define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000
142 #define CONFIG_SYS_RCAR_I2C0_SPEED 400000
143 #define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000
144 #define CONFIG_SYS_RCAR_I2C1_SPEED 400000
145 #define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000
146 #define CONFIG_SYS_RCAR_I2C2_SPEED 400000
147 #define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000
148 #define CONFIG_SYS_RCAR_I2C3_SPEED 400000
149 #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
151 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
154 #define RMOBILE_XTAL_CLK 20000000u
155 #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
156 #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
157 #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
158 #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
159 #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
160 #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
161 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ
163 #define CONFIG_SYS_TMU_CLK_DIV 4
165 #endif /* __LAGER_H */