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[u-boot] / include / configs / ls1021aiot.h
1 /*
2  * Copyright 2016 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
11
12 #define CONFIG_SYS_FSL_CLK
13
14 /*
15  * Size of malloc() pool
16  */
17 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
18
19 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
20 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
21
22 #define CONFIG_SYS_CLK_FREQ             100000000
23 #define CONFIG_DDR_CLK_FREQ             100000000
24
25 /*
26  * DDR: 800 MHz ( 1600 MT/s data rate )
27  */
28
29 #define DDR_SDRAM_CFG                   0x470c0008
30 #define DDR_CS0_BNDS                    0x008000bf
31 #define DDR_CS0_CONFIG                  0x80014302
32 #define DDR_TIMING_CFG_0                0x50550004
33 #define DDR_TIMING_CFG_1                0xbcb38c56
34 #define DDR_TIMING_CFG_2                0x0040d120
35 #define DDR_TIMING_CFG_3                0x010e1000
36 #define DDR_TIMING_CFG_4                0x00000001
37 #define DDR_TIMING_CFG_5                0x03401400
38 #define DDR_SDRAM_CFG_2                 0x00401010
39 #define DDR_SDRAM_MODE                  0x00061c60
40 #define DDR_SDRAM_MODE_2                0x00180000
41 #define DDR_SDRAM_INTERVAL              0x18600618
42 #define DDR_DDR_WRLVL_CNTL              0x8655f605
43 #define DDR_DDR_WRLVL_CNTL_2    0x05060607
44 #define DDR_DDR_WRLVL_CNTL_3    0x05050505
45 #define DDR_DDR_CDR1                    0x80040000
46 #define DDR_DDR_CDR2                    0x00000001
47 #define DDR_SDRAM_CLK_CNTL              0x02000000
48 #define DDR_DDR_ZQ_CNTL                 0x89080600
49 #define DDR_CS0_CONFIG_2                0
50 #define DDR_SDRAM_CFG_MEM_EN    0x80000000
51 #define SDRAM_CFG2_D_INIT               0x00000010
52 #define DDR_CDR2_VREF_TRAIN_EN  0x00000080
53 #define SDRAM_CFG2_FRC_SR               0x80000000
54 #define SDRAM_CFG_BI                    0x00000001
55
56 #ifdef CONFIG_RAMBOOT_PBL
57 #define CONFIG_SYS_FSL_PBL_PBI  \
58         board/freescale/ls1021aiot/ls102xa_pbi.cfg
59 #endif
60
61 #ifdef CONFIG_SD_BOOT
62 #define CONFIG_SYS_FSL_PBL_RCW  \
63         board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
64 #define CONFIG_SPL_FRAMEWORK
65 #define CONFIG_SPL_LIBCOMMON_SUPPORT
66 #define CONFIG_SPL_LIBGENERIC_SUPPORT
67 #define CONFIG_SPL_ENV_SUPPORT
68 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
69 #define CONFIG_SPL_I2C_SUPPORT
70 #define CONFIG_SPL_WATCHDOG_SUPPORT
71 #define CONFIG_SPL_SERIAL_SUPPORT
72 #define CONFIG_SPL_MMC_SUPPORT
73 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
74
75 #define CONFIG_SPL_TEXT_BASE    0x10000000
76 #define CONFIG_SPL_MAX_SIZE             0x1a000
77 #define CONFIG_SPL_STACK                0x1001d000
78 #define CONFIG_SPL_PAD_TO               0x1c000
79
80 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
81                 CONFIG_SYS_MONITOR_LEN)
82 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
83 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
84 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
85 #define CONFIG_SYS_MONITOR_LEN          0x80000
86 #endif
87
88 #define CONFIG_NR_DRAM_BANKS            1
89
90 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
91 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
92
93 /*
94  * Serial Port
95  */
96 #define CONFIG_CONS_INDEX               1
97 #define CONFIG_SYS_NS16550_SERIAL
98 #define CONFIG_SYS_NS16550_REG_SIZE     1
99 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
100
101 /*
102  * I2C
103  */
104 #define CONFIG_CMD_I2C
105 #define CONFIG_SYS_I2C
106 #define CONFIG_SYS_I2C_MXC
107 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
108 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
109 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
110
111 /* EEPROM */
112 #define CONFIG_ID_EEPROM
113 #define CONFIG_SYS_I2C_EEPROM_NXID
114 #define CONFIG_SYS_EEPROM_BUS_NUM               0
115 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x51
116 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
117
118 /*
119  * MMC
120  */
121 #define CONFIG_CMD_MMC
122 #define CONFIG_FSL_ESDHC
123
124 /* SATA */
125 #define CONFIG_SCSI_AHCI_PLAT
126 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
127 #define PCI_DEVICE_ID_FREESCALE_AHCI    0x0440
128 #endif
129 #define CONFIG_SCSI_DEV_LIST            {PCI_VENDOR_ID_FREESCALE, \
130         PCI_DEVICE_ID_FREESCALE_AHCI}
131
132 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     1
133 #define CONFIG_SYS_SCSI_MAX_LUN         1
134 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
135                 CONFIG_SYS_SCSI_MAX_LUN)
136
137 /* SPI */
138 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
139 #define CONFIG_SPI_FLASH_SPANSION
140
141 /* QSPI */
142 #define QSPI0_AMBA_BASE                 0x40000000
143 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
144 #define FSL_QSPI_FLASH_NUM              2
145 #define CONFIG_SPI_FLASH_BAR
146 #define CONFIG_SPI_FLASH_SPANSION
147 #endif
148
149 /* DM SPI */
150 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
151 #define CONFIG_CMD_SF
152 #define CONFIG_DM_SPI_FLASH
153 #endif
154
155 /*
156  * eTSEC
157  */
158 #define CONFIG_TSEC_ENET
159
160 #ifdef CONFIG_TSEC_ENET
161 #define CONFIG_MII
162 #define CONFIG_MII_DEFAULT_TSEC         1
163 #define CONFIG_TSEC1                    1
164 #define CONFIG_TSEC1_NAME               "eTSEC1"
165 #define CONFIG_TSEC2                    1
166 #define CONFIG_TSEC2_NAME               "eTSEC2"
167
168 #define TSEC1_PHY_ADDR                  1
169 #define TSEC2_PHY_ADDR                  3
170
171 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
172 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
173
174 #define TSEC1_PHYIDX                    0
175 #define TSEC2_PHYIDX                    0
176
177 #define CONFIG_ETHPRIME                 "eTSEC2"
178
179 #define CONFIG_PHY_ATHEROS
180
181 #define CONFIG_HAS_ETH0
182 #define CONFIG_HAS_ETH1
183 #define CONFIG_HAS_ETH2
184 #endif
185
186 /* PCIe */
187 #define CONFIG_PCIE1            /* PCIE controler 1 */
188 #define CONFIG_PCIE2            /* PCIE controler 2 */
189
190 #define FSL_PCIE_COMPAT         "fsl,ls1021a-pcie"
191
192 #ifdef CONFIG_PCI
193 #define CONFIG_PCI_SCAN_SHOW
194 #endif
195
196 #define CONFIG_CMD_PING
197 #define CONFIG_CMD_DHCP
198 #define CONFIG_CMD_MII
199
200 #define CONFIG_CMDLINE_TAG
201 #define CONFIG_CMDLINE_EDITING
202
203 #define CONFIG_PEN_ADDR_BIG_ENDIAN
204 #define CONFIG_LAYERSCAPE_NS_ACCESS
205 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
206 #define COUNTER_FREQUENCY               12500000
207
208 #define CONFIG_HWCONFIG
209 #define HWCONFIG_BUFFER_SIZE            256
210
211 #define CONFIG_FSL_DEVICE_DISABLE
212
213 #define CONFIG_EXTRA_ENV_SETTINGS       \
214         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
215 "initrd_high=0xffffffff\0"      \
216 "fdt_high=0xffffffff\0"
217
218 /*
219  * Miscellaneous configurable options
220  */
221 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
222 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
223 #define CONFIG_AUTO_COMPLETE
224
225 #define CONFIG_CMD_GREPENV
226 #define CONFIG_CMD_MEMINFO
227
228 #define CONFIG_SYS_LOAD_ADDR            0x82000000
229
230 #define CONFIG_LS102XA_STREAM_ID
231
232 #define CONFIG_SYS_INIT_SP_OFFSET \
233         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
234 #define CONFIG_SYS_INIT_SP_ADDR \
235         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
236
237 #ifdef CONFIG_SPL_BUILD
238 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
239 #else
240 /* start of monitor */
241 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
242 #endif
243
244 #define CONFIG_SYS_QE_FW_ADDR   0x67f40000
245
246 /*
247  * Environment
248  */
249
250 #define CONFIG_ENV_OVERWRITE
251
252 #if defined(CONFIG_SD_BOOT)
253 #define CONFIG_ENV_OFFSET               0x100000
254 #define CONFIG_SYS_MMC_ENV_DEV  0
255 #define CONFIG_ENV_SIZE                 0x2000
256 #elif defined(CONFIG_QSPI_BOOT)
257 #define CONFIG_ENV_SIZE                 0x2000
258 #define CONFIG_ENV_OFFSET               0x100000
259 #define CONFIG_ENV_SECT_SIZE    0x10000
260 #endif
261
262 #define CONFIG_OF_BOARD_SETUP
263 #define CONFIG_OF_STDOUT_VIA_ALIAS
264
265 #define CONFIG_MISC_INIT_R
266
267 #include <asm/fsl_secure_boot.h>
268
269 #endif