2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_LS102XA
12 #define CONFIG_ARMV7_PSCI_1_0
14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
16 #define CONFIG_SYS_FSL_CLK
18 #define CONFIG_DISPLAY_CPUINFO
19 #define CONFIG_DISPLAY_BOARDINFO
21 #define CONFIG_BOARD_EARLY_INIT_F
23 #define CONFIG_DEEP_SLEEP
24 #if defined(CONFIG_DEEP_SLEEP)
25 #define CONFIG_SILENT_CONSOLE
29 * Size of malloc() pool
31 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
33 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
34 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
37 * Generic Timer Definitions
39 #define GENERIC_TIMER_CLK 12500000
42 unsigned long get_board_sys_clk(void);
43 unsigned long get_board_ddr_clk(void);
46 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
47 #define CONFIG_SYS_CLK_FREQ 100000000
48 #define CONFIG_DDR_CLK_FREQ 100000000
49 #define CONFIG_QIXIS_I2C_ACCESS
51 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
52 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
55 #ifdef CONFIG_RAMBOOT_PBL
56 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
60 #ifdef CONFIG_SD_BOOT_QSPI
61 #define CONFIG_SYS_FSL_PBL_RCW \
62 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
64 #define CONFIG_SYS_FSL_PBL_RCW \
65 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
67 #define CONFIG_SPL_FRAMEWORK
68 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
69 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
70 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600
72 #define CONFIG_SPL_TEXT_BASE 0x10000000
73 #define CONFIG_SPL_MAX_SIZE 0x1a000
74 #define CONFIG_SPL_STACK 0x1001d000
75 #define CONFIG_SPL_PAD_TO 0x1c000
76 #define CONFIG_SYS_TEXT_BASE 0x82000000
78 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
79 CONFIG_SYS_MONITOR_LEN)
80 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
81 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
82 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
83 #define CONFIG_SYS_MONITOR_LEN 0xc0000
86 #ifdef CONFIG_QSPI_BOOT
87 #define CONFIG_SYS_TEXT_BASE 0x40010000
90 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
91 #define CONFIG_SYS_NO_FLASH
94 #ifdef CONFIG_NAND_BOOT
95 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
96 #define CONFIG_SPL_FRAMEWORK
97 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
99 #define CONFIG_SPL_TEXT_BASE 0x10000000
100 #define CONFIG_SPL_MAX_SIZE 0x1a000
101 #define CONFIG_SPL_STACK 0x1001d000
102 #define CONFIG_SPL_PAD_TO 0x1c000
103 #define CONFIG_SYS_TEXT_BASE 0x82000000
105 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
106 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
107 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
108 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
109 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
111 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
112 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
113 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
114 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
115 #define CONFIG_SYS_MONITOR_LEN 0x80000
118 #ifndef CONFIG_SYS_TEXT_BASE
119 #define CONFIG_SYS_TEXT_BASE 0x60100000
122 #define CONFIG_NR_DRAM_BANKS 1
124 #define CONFIG_DDR_SPD
125 #define SPD_EEPROM_ADDRESS 0x51
126 #define CONFIG_SYS_SPD_BUS_NUM 0
128 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
129 #ifndef CONFIG_SYS_FSL_DDR4
130 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
131 #define CONFIG_SYS_DDR_RAW_TIMING
133 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
134 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
136 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
137 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
139 #define CONFIG_DDR_ECC
140 #ifdef CONFIG_DDR_ECC
141 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
142 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
145 #define CONFIG_FSL_CAAM /* Enable CAAM */
147 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
148 !defined(CONFIG_QSPI_BOOT)
155 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
156 #define CONFIG_FSL_IFC
157 #define CONFIG_SYS_FLASH_BASE 0x60000000
158 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
160 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
161 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
162 CSPR_PORT_SIZE_16 | \
165 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
166 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
168 CSPR_PORT_SIZE_16 | \
171 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
173 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
175 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
176 FTIM0_NOR_TEADC(0x5) | \
177 FTIM0_NOR_TEAHC(0x5))
178 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
179 FTIM1_NOR_TRAD_NOR(0x1a) | \
180 FTIM1_NOR_TSEQRAD_NOR(0x13))
181 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
182 FTIM2_NOR_TCH(0x4) | \
183 FTIM2_NOR_TWPH(0xe) | \
185 #define CONFIG_SYS_NOR_FTIM3 0
187 #define CONFIG_FLASH_CFI_DRIVER
188 #define CONFIG_SYS_FLASH_CFI
189 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
190 #define CONFIG_SYS_FLASH_QUIET_TEST
191 #define CONFIG_FLASH_SHOW_PROGRESS 45
192 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
193 #define CONFIG_SYS_WRITE_SWAPPED_DATA
195 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
196 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
197 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
198 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
200 #define CONFIG_SYS_FLASH_EMPTY_INFO
201 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
202 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
205 * NAND Flash Definitions
207 #define CONFIG_NAND_FSL_IFC
209 #define CONFIG_SYS_NAND_BASE 0x7e800000
210 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
212 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
214 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
218 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
219 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
220 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
221 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
222 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
223 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
224 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
225 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
227 #define CONFIG_SYS_NAND_ONFI_DETECTION
229 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
230 FTIM0_NAND_TWP(0x18) | \
231 FTIM0_NAND_TWCHT(0x7) | \
233 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
234 FTIM1_NAND_TWBE(0x39) | \
235 FTIM1_NAND_TRR(0xe) | \
236 FTIM1_NAND_TRP(0x18))
237 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
238 FTIM2_NAND_TREH(0xa) | \
239 FTIM2_NAND_TWHRE(0x1e))
240 #define CONFIG_SYS_NAND_FTIM3 0x0
242 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
243 #define CONFIG_SYS_MAX_NAND_DEVICE 1
244 #define CONFIG_CMD_NAND
246 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
252 #define CONFIG_FSL_QIXIS
254 #ifdef CONFIG_FSL_QIXIS
255 #define QIXIS_BASE 0x7fb00000
256 #define QIXIS_BASE_PHYS QIXIS_BASE
257 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
258 #define QIXIS_LBMAP_SWITCH 6
259 #define QIXIS_LBMAP_MASK 0x0f
260 #define QIXIS_LBMAP_SHIFT 0
261 #define QIXIS_LBMAP_DFLTBANK 0x00
262 #define QIXIS_LBMAP_ALTBANK 0x04
263 #define QIXIS_PWR_CTL 0x21
264 #define QIXIS_PWR_CTL_POWEROFF 0x80
265 #define QIXIS_RST_CTL_RESET 0x44
266 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
267 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
268 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
269 #define QIXIS_CTL_SYS 0x5
270 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
271 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
272 #define QIXIS_RST_FORCE_3 0x45
273 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
274 #define QIXIS_PWR_CTL2 0x21
275 #define QIXIS_PWR_CTL2_PCTL 0x2
277 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
278 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
282 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
283 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
284 CSOR_NOR_NOR_MODE_AVD_NOR | \
288 * QIXIS Timing parameters for IFC GPCM
290 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
291 FTIM0_GPCM_TEADC(0xe) | \
292 FTIM0_GPCM_TEAHC(0xe))
293 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
294 FTIM1_GPCM_TRAD(0x1f))
295 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
296 FTIM2_GPCM_TCH(0xe) | \
297 FTIM2_GPCM_TWP(0xf0))
298 #define CONFIG_SYS_FPGA_FTIM3 0x0
301 #if defined(CONFIG_NAND_BOOT)
302 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
303 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
304 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
305 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
306 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
307 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
308 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
309 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
310 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
311 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
312 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
313 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
314 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
315 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
316 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
317 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
318 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
319 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
320 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
321 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
322 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
323 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
324 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
325 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
326 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
327 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
328 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
329 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
330 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
331 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
332 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
333 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
335 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
336 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
337 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
338 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
339 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
340 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
341 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
342 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
343 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
344 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
345 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
346 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
347 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
348 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
349 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
350 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
351 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
352 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
353 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
354 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
355 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
356 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
357 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
358 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
359 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
360 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
361 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
362 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
363 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
364 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
365 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
366 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
373 #define CONFIG_LPUART_32B_REG
375 #define CONFIG_CONS_INDEX 1
376 #define CONFIG_SYS_NS16550_SERIAL
377 #ifndef CONFIG_DM_SERIAL
378 #define CONFIG_SYS_NS16550_REG_SIZE 1
380 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
383 #define CONFIG_BAUDRATE 115200
388 #define CONFIG_SYS_I2C
389 #define CONFIG_SYS_I2C_MXC
390 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
391 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
392 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
395 * I2C bus multiplexer
397 #define I2C_MUX_PCA_ADDR_PRI 0x77
398 #define I2C_MUX_CH_DEFAULT 0x8
399 #define I2C_MUX_CH_CH7301 0xC
405 #define CONFIG_FSL_ESDHC
406 #define CONFIG_GENERIC_MMC
408 #define CONFIG_DOS_PARTITION
411 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
413 #define QSPI0_AMBA_BASE 0x40000000
414 #define FSL_QSPI_FLASH_SIZE (1 << 24)
415 #define FSL_QSPI_FLASH_NUM 2
420 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
421 #define CONFIG_DM_SPI_FLASH
422 #define CONFIG_SPI_FLASH_DATAFLASH
429 /* EHCI Support - disbaled by default */
430 /*#define CONFIG_HAS_FSL_DR_USB*/
432 #ifdef CONFIG_HAS_FSL_DR_USB
433 #define CONFIG_USB_EHCI
434 #define CONFIG_USB_EHCI_FSL
435 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
438 /*XHCI Support - enabled by default*/
439 #define CONFIG_HAS_FSL_XHCI_USB
441 #ifdef CONFIG_HAS_FSL_XHCI_USB
442 #define CONFIG_USB_XHCI_FSL
443 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
444 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
450 #define CONFIG_FSL_DCU_FB
452 #ifdef CONFIG_FSL_DCU_FB
454 #define CONFIG_CMD_BMP
455 #define CONFIG_CFB_CONSOLE
456 #define CONFIG_VGA_AS_SINGLE_DEVICE
457 #define CONFIG_VIDEO_LOGO
458 #define CONFIG_VIDEO_BMP_LOGO
459 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
461 #define CONFIG_FSL_DIU_CH7301
462 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
463 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
464 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
470 #define CONFIG_TSEC_ENET
472 #ifdef CONFIG_TSEC_ENET
474 #define CONFIG_MII_DEFAULT_TSEC 3
475 #define CONFIG_TSEC1 1
476 #define CONFIG_TSEC1_NAME "eTSEC1"
477 #define CONFIG_TSEC2 1
478 #define CONFIG_TSEC2_NAME "eTSEC2"
479 #define CONFIG_TSEC3 1
480 #define CONFIG_TSEC3_NAME "eTSEC3"
482 #define TSEC1_PHY_ADDR 1
483 #define TSEC2_PHY_ADDR 2
484 #define TSEC3_PHY_ADDR 3
486 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
487 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
488 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
490 #define TSEC1_PHYIDX 0
491 #define TSEC2_PHYIDX 0
492 #define TSEC3_PHYIDX 0
494 #define CONFIG_ETHPRIME "eTSEC1"
496 #define CONFIG_PHY_GIGE
497 #define CONFIG_PHYLIB
498 #define CONFIG_PHY_REALTEK
500 #define CONFIG_HAS_ETH0
501 #define CONFIG_HAS_ETH1
502 #define CONFIG_HAS_ETH2
504 #define CONFIG_FSL_SGMII_RISER 1
505 #define SGMII_RISER_PHY_OFFSET 0x1b
507 #ifdef CONFIG_FSL_SGMII_RISER
508 #define CONFIG_SYS_TBIPA_VALUE 8
514 #define CONFIG_PCI /* Enable PCI/PCIE */
515 #define CONFIG_PCIE1 /* PCIE controller 1 */
516 #define CONFIG_PCIE2 /* PCIE controller 2 */
517 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
518 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
520 #define CONFIG_SYS_PCI_64BIT
522 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
523 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
524 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
525 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
527 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
528 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
529 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
531 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
532 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
533 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
536 #define CONFIG_PCI_PNP
537 #define CONFIG_PCI_SCAN_SHOW
538 #define CONFIG_CMD_PCI
541 #define CONFIG_CMDLINE_TAG
542 #define CONFIG_CMDLINE_EDITING
544 #define CONFIG_PEN_ADDR_BIG_ENDIAN
545 #define CONFIG_LAYERSCAPE_NS_ACCESS
546 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
547 #define CONFIG_TIMER_CLK_FREQ 12500000
549 #define CONFIG_HWCONFIG
550 #define HWCONFIG_BUFFER_SIZE 256
552 #define CONFIG_FSL_DEVICE_DISABLE
555 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000
558 #define CONFIG_EXTRA_ENV_SETTINGS \
559 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
560 "fdt_high=0xffffffff\0" \
561 "initrd_high=0xffffffff\0" \
562 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
564 #define CONFIG_EXTRA_ENV_SETTINGS \
565 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
566 "fdt_high=0xffffffff\0" \
567 "initrd_high=0xffffffff\0" \
568 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
572 * Miscellaneous configurable options
574 #define CONFIG_SYS_LONGHELP /* undef to save memory */
575 #define CONFIG_AUTO_COMPLETE
576 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
577 #define CONFIG_SYS_PBSIZE \
578 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
579 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
580 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
582 #define CONFIG_SYS_MEMTEST_START 0x80000000
583 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
585 #define CONFIG_SYS_LOAD_ADDR 0x82000000
587 #define CONFIG_LS102XA_STREAM_ID
591 * The stack sizes are set up in start.S using the settings below
593 #define CONFIG_STACKSIZE (30 * 1024)
595 #define CONFIG_SYS_INIT_SP_OFFSET \
596 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
597 #define CONFIG_SYS_INIT_SP_ADDR \
598 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
600 #ifdef CONFIG_SPL_BUILD
601 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
603 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
609 #define CONFIG_ENV_OVERWRITE
611 #if defined(CONFIG_SD_BOOT)
612 #define CONFIG_ENV_OFFSET 0x100000
613 #define CONFIG_ENV_IS_IN_MMC
614 #define CONFIG_SYS_MMC_ENV_DEV 0
615 #define CONFIG_ENV_SIZE 0x2000
616 #elif defined(CONFIG_QSPI_BOOT)
617 #define CONFIG_ENV_IS_IN_SPI_FLASH
618 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
619 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
620 #define CONFIG_ENV_SECT_SIZE 0x10000
621 #elif defined(CONFIG_NAND_BOOT)
622 #define CONFIG_ENV_IS_IN_NAND
623 #define CONFIG_ENV_SIZE 0x2000
624 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
626 #define CONFIG_ENV_IS_IN_FLASH
627 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
628 #define CONFIG_ENV_SIZE 0x2000
629 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
632 #define CONFIG_MISC_INIT_R
634 /* Hash command with SHA acceleration supported in hardware */
635 #ifdef CONFIG_FSL_CAAM
636 #define CONFIG_CMD_HASH
637 #define CONFIG_SHA_HW_ACCEL
640 #include <asm/fsl_secure_boot.h>
641 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */