2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_ARMV7_PSCI_1_0
12 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
14 #define CONFIG_SYS_FSL_CLK
16 #define CONFIG_SKIP_LOWLEVEL_INIT
17 #define CONFIG_DEEP_SLEEP
20 * Size of malloc() pool
22 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
24 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
25 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
32 * EHCI Support - disbaled by default as
33 * there is no signal coming out of soc on
34 * this board for this controller. However,
35 * the silicon still has this controller,
36 * and anyone can use this controller by
37 * taking signals out on their board.
40 /*#define CONFIG_HAS_FSL_DR_USB*/
42 #ifdef CONFIG_HAS_FSL_DR_USB
43 #define CONFIG_USB_EHCI_FSL
44 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
47 /* XHCI Support - enabled by default */
48 #define CONFIG_HAS_FSL_XHCI_USB
50 #ifdef CONFIG_HAS_FSL_XHCI_USB
51 #define CONFIG_USB_XHCI_FSL
52 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
55 #define CONFIG_SYS_CLK_FREQ 100000000
56 #define CONFIG_DDR_CLK_FREQ 100000000
58 #define DDR_SDRAM_CFG 0x470c0008
59 #define DDR_CS0_BNDS 0x008000bf
60 #define DDR_CS0_CONFIG 0x80014302
61 #define DDR_TIMING_CFG_0 0x50550004
62 #define DDR_TIMING_CFG_1 0xbcb38c56
63 #define DDR_TIMING_CFG_2 0x0040d120
64 #define DDR_TIMING_CFG_3 0x010e1000
65 #define DDR_TIMING_CFG_4 0x00000001
66 #define DDR_TIMING_CFG_5 0x03401400
67 #define DDR_SDRAM_CFG_2 0x00401010
68 #define DDR_SDRAM_MODE 0x00061c60
69 #define DDR_SDRAM_MODE_2 0x00180000
70 #define DDR_SDRAM_INTERVAL 0x18600618
71 #define DDR_DDR_WRLVL_CNTL 0x8655f605
72 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
73 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
74 #define DDR_DDR_CDR1 0x80040000
75 #define DDR_DDR_CDR2 0x00000001
76 #define DDR_SDRAM_CLK_CNTL 0x02000000
77 #define DDR_DDR_ZQ_CNTL 0x89080600
78 #define DDR_CS0_CONFIG_2 0
79 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
80 #define SDRAM_CFG2_D_INIT 0x00000010
81 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
82 #define SDRAM_CFG2_FRC_SR 0x80000000
83 #define SDRAM_CFG_BI 0x00000001
85 #ifdef CONFIG_RAMBOOT_PBL
86 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
90 #ifdef CONFIG_SD_BOOT_QSPI
91 #define CONFIG_SYS_FSL_PBL_RCW \
92 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
94 #define CONFIG_SYS_FSL_PBL_RCW \
95 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
97 #define CONFIG_SPL_FRAMEWORK
98 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
100 #ifdef CONFIG_SECURE_BOOT
102 * HDR would be appended at end of image and copied to DDR along
105 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
106 #endif /* ifdef CONFIG_SECURE_BOOT */
108 #define CONFIG_SPL_TEXT_BASE 0x10000000
109 #define CONFIG_SPL_MAX_SIZE 0x1a000
110 #define CONFIG_SPL_STACK 0x1001d000
111 #define CONFIG_SPL_PAD_TO 0x1c000
112 #define CONFIG_SYS_TEXT_BASE 0x82000000
114 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
115 CONFIG_SYS_MONITOR_LEN)
116 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
117 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
118 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
120 #ifdef CONFIG_U_BOOT_HDR_SIZE
122 * HDR would be appended at end of image and copied to DDR along
123 * with U-Boot image. Here u-boot max. size is 512K. So if binary
124 * size increases then increase this size in case of secure boot as
125 * it uses raw u-boot image instead of fit image.
127 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
129 #define CONFIG_SYS_MONITOR_LEN 0x100000
130 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
133 #ifdef CONFIG_QSPI_BOOT
134 #define CONFIG_SYS_TEXT_BASE 0x40100000
137 #ifndef CONFIG_SYS_TEXT_BASE
138 #define CONFIG_SYS_TEXT_BASE 0x60100000
141 #define CONFIG_NR_DRAM_BANKS 1
142 #define PHYS_SDRAM 0x80000000
143 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
145 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
146 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
148 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
149 !defined(CONFIG_QSPI_BOOT)
151 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
157 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
158 #define CONFIG_FSL_IFC
159 #define CONFIG_SYS_FLASH_BASE 0x60000000
160 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
162 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
163 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
164 CSPR_PORT_SIZE_16 | \
167 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
169 /* NOR Flash Timing Params */
170 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
172 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
173 FTIM0_NOR_TEADC(0x5) | \
174 FTIM0_NOR_TAVDS(0x0) | \
175 FTIM0_NOR_TEAHC(0x5))
176 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
177 FTIM1_NOR_TRAD_NOR(0x1A) | \
178 FTIM1_NOR_TSEQRAD_NOR(0x13))
179 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
180 FTIM2_NOR_TCH(0x4) | \
181 FTIM2_NOR_TWP(0x1c) | \
182 FTIM2_NOR_TWPH(0x0e))
183 #define CONFIG_SYS_NOR_FTIM3 0
185 #define CONFIG_FLASH_CFI_DRIVER
186 #define CONFIG_SYS_FLASH_CFI
187 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
188 #define CONFIG_SYS_FLASH_QUIET_TEST
189 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
191 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
192 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
193 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
194 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
196 #define CONFIG_SYS_FLASH_EMPTY_INFO
197 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
199 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
200 #define CONFIG_SYS_WRITE_SWAPPED_DATA
205 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
206 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
208 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
209 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
213 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
214 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
215 CSOR_NOR_NOR_MODE_AVD_NOR | \
218 /* CPLD Timing parameters for IFC GPCM */
219 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
220 FTIM0_GPCM_TEADC(0xf) | \
221 FTIM0_GPCM_TEAHC(0xf))
222 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
223 FTIM1_GPCM_TRAD(0x3f))
224 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
225 FTIM2_GPCM_TCH(0xf) | \
226 FTIM2_GPCM_TWP(0xff))
227 #define CONFIG_SYS_FPGA_FTIM3 0x0
228 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
229 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
230 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
231 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
232 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
233 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
234 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
235 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
236 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
237 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
238 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
239 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
240 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
241 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
242 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
243 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
249 #define CONFIG_LPUART_32B_REG
251 #define CONFIG_CONS_INDEX 1
252 #define CONFIG_SYS_NS16550_SERIAL
253 #ifndef CONFIG_DM_SERIAL
254 #define CONFIG_SYS_NS16550_REG_SIZE 1
256 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
262 #define CONFIG_SYS_I2C
263 #define CONFIG_SYS_I2C_MXC
264 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
265 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
266 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
269 #define CONFIG_ID_EEPROM
270 #define CONFIG_SYS_I2C_EEPROM_NXID
271 #define CONFIG_SYS_EEPROM_BUS_NUM 1
272 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
273 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
274 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
275 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
280 #define CONFIG_FSL_ESDHC
283 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
285 #define QSPI0_AMBA_BASE 0x40000000
286 #define FSL_QSPI_FLASH_SIZE (1 << 24)
287 #define FSL_QSPI_FLASH_NUM 2
293 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
294 #define CONFIG_DM_SPI_FLASH
300 #ifdef CONFIG_VIDEO_FSL_DCU_FB
301 #define CONFIG_VIDEO_LOGO
302 #define CONFIG_VIDEO_BMP_LOGO
304 #define CONFIG_FSL_DCU_SII9022A
305 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
306 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
312 #define CONFIG_TSEC_ENET
314 #ifdef CONFIG_TSEC_ENET
316 #define CONFIG_MII_DEFAULT_TSEC 1
317 #define CONFIG_TSEC1 1
318 #define CONFIG_TSEC1_NAME "eTSEC1"
319 #define CONFIG_TSEC2 1
320 #define CONFIG_TSEC2_NAME "eTSEC2"
321 #define CONFIG_TSEC3 1
322 #define CONFIG_TSEC3_NAME "eTSEC3"
324 #define TSEC1_PHY_ADDR 2
325 #define TSEC2_PHY_ADDR 0
326 #define TSEC3_PHY_ADDR 1
328 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
329 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
330 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
332 #define TSEC1_PHYIDX 0
333 #define TSEC2_PHYIDX 0
334 #define TSEC3_PHYIDX 0
336 #define CONFIG_ETHPRIME "eTSEC1"
338 #define CONFIG_PHY_GIGE
339 #define CONFIG_PHY_ATHEROS
341 #define CONFIG_HAS_ETH0
342 #define CONFIG_HAS_ETH1
343 #define CONFIG_HAS_ETH2
347 #define CONFIG_PCIE1 /* PCIE controller 1 */
348 #define CONFIG_PCIE2 /* PCIE controller 2 */
351 #define CONFIG_PCI_SCAN_SHOW
352 #define CONFIG_CMD_PCI
355 #define CONFIG_CMDLINE_TAG
357 #define CONFIG_PEN_ADDR_BIG_ENDIAN
358 #define CONFIG_LAYERSCAPE_NS_ACCESS
359 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
360 #define COUNTER_FREQUENCY 12500000
362 #define CONFIG_HWCONFIG
363 #define HWCONFIG_BUFFER_SIZE 256
365 #define CONFIG_FSL_DEVICE_DISABLE
367 #include <config_distro_defaults.h>
368 #define BOOT_TARGET_DEVICES(func) \
371 #include <config_distro_bootcmd.h>
374 #define CONFIG_EXTRA_ENV_SETTINGS \
375 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
376 "initrd_high=0xffffffff\0" \
377 "fdt_high=0xffffffff\0" \
378 "fdt_addr=0x64f00000\0" \
379 "kernel_addr=0x65000000\0" \
380 "scriptaddr=0x80000000\0" \
381 "scripthdraddr=0x80080000\0" \
382 "fdtheader_addr_r=0x80100000\0" \
383 "kernelheader_addr_r=0x80200000\0" \
384 "kernel_addr_r=0x81000000\0" \
385 "fdt_addr_r=0x90000000\0" \
386 "ramdisk_addr_r=0xa0000000\0" \
387 "load_addr=0xa0000000\0" \
388 "kernel_size=0x2800000\0" \
390 "boot_scripts=ls1021atwr_boot.scr\0" \
391 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
392 "scan_dev_for_boot_part=" \
393 "part list ${devtype} ${devnum} devplist; " \
394 "env exists devplist || setenv devplist 1; " \
395 "for distro_bootpart in ${devplist}; do " \
396 "if fstype ${devtype} " \
397 "${devnum}:${distro_bootpart} " \
398 "bootfstype; then " \
399 "run scan_dev_for_boot; " \
402 "scan_dev_for_boot=" \
403 "echo Scanning ${devtype} " \
404 "${devnum}:${distro_bootpart}...; " \
405 "for prefix in ${boot_prefixes}; do " \
406 "run scan_dev_for_scripts; " \
410 "load ${devtype} ${devnum}:${distro_bootpart} " \
411 "${scriptaddr} ${prefix}${script}; " \
412 "env exists secureboot && load ${devtype} " \
413 "${devnum}:${distro_bootpart} " \
414 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
415 "&& esbc_validate ${scripthdraddr};" \
416 "source ${scriptaddr}\0" \
417 "installer=load mmc 0:2 $load_addr " \
418 "/flex_installer_arm32.itb; " \
419 "bootm $load_addr#ls1021atwr\0" \
420 "qspi_bootcmd=echo Trying load from qspi..;" \
421 "sf probe && sf read $load_addr " \
422 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
423 "nor_bootcmd=echo Trying load from nor..;" \
424 "cp.b $kernel_addr $load_addr " \
425 "$kernel_size && bootm $load_addr#$board\0"
427 #define CONFIG_EXTRA_ENV_SETTINGS \
428 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
429 "initrd_high=0xffffffff\0" \
430 "fdt_high=0xffffffff\0" \
431 "fdt_addr=0x64f00000\0" \
432 "kernel_addr=0x65000000\0" \
433 "scriptaddr=0x80000000\0" \
434 "scripthdraddr=0x80080000\0" \
435 "fdtheader_addr_r=0x80100000\0" \
436 "kernelheader_addr_r=0x80200000\0" \
437 "kernel_addr_r=0x81000000\0" \
438 "fdt_addr_r=0x90000000\0" \
439 "ramdisk_addr_r=0xa0000000\0" \
440 "load_addr=0xa0000000\0" \
441 "kernel_size=0x2800000\0" \
443 "boot_scripts=ls1021atwr_boot.scr\0" \
444 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
445 "scan_dev_for_boot_part=" \
446 "part list ${devtype} ${devnum} devplist; " \
447 "env exists devplist || setenv devplist 1; " \
448 "for distro_bootpart in ${devplist}; do " \
449 "if fstype ${devtype} " \
450 "${devnum}:${distro_bootpart} " \
451 "bootfstype; then " \
452 "run scan_dev_for_boot; " \
455 "scan_dev_for_boot=" \
456 "echo Scanning ${devtype} " \
457 "${devnum}:${distro_bootpart}...; " \
458 "for prefix in ${boot_prefixes}; do " \
459 "run scan_dev_for_scripts; " \
463 "load ${devtype} ${devnum}:${distro_bootpart} " \
464 "${scriptaddr} ${prefix}${script}; " \
465 "env exists secureboot && load ${devtype} " \
466 "${devnum}:${distro_bootpart} " \
467 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
468 "&& esbc_validate ${scripthdraddr};" \
469 "source ${scriptaddr}\0" \
470 "installer=load mmc 0:2 $load_addr " \
471 "/flex_installer_arm32.itb; " \
472 "bootm $load_addr#ls1021atwr\0" \
473 "qspi_bootcmd=echo Trying load from qspi..;" \
474 "sf probe && sf read $load_addr " \
475 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
476 "nor_bootcmd=echo Trying load from nor..;" \
477 "cp.b $kernel_addr $load_addr " \
478 "$kernel_size && bootm $load_addr#$board\0"
481 #undef CONFIG_BOOTCOMMAND
482 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
483 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
484 "&& esbc_halt; run qspi_bootcmd;"
486 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
487 "&& esbc_halt; run nor_bootcmd;"
490 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0"
493 * Miscellaneous configurable options
495 #define CONFIG_SYS_LONGHELP /* undef to save memory */
496 #define CONFIG_AUTO_COMPLETE
497 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
498 #define CONFIG_SYS_PBSIZE \
499 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
500 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
501 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
503 #define CONFIG_SYS_MEMTEST_START 0x80000000
504 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
506 #define CONFIG_SYS_LOAD_ADDR 0x82000000
508 #define CONFIG_LS102XA_STREAM_ID
510 #define CONFIG_SYS_INIT_SP_OFFSET \
511 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
512 #define CONFIG_SYS_INIT_SP_ADDR \
513 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
515 #ifdef CONFIG_SPL_BUILD
516 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
518 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
521 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
526 #define CONFIG_ENV_OVERWRITE
528 #if defined(CONFIG_SD_BOOT)
529 #define CONFIG_ENV_OFFSET 0x300000
530 #define CONFIG_SYS_MMC_ENV_DEV 0
531 #define CONFIG_ENV_SIZE 0x20000
532 #elif defined(CONFIG_QSPI_BOOT)
533 #define CONFIG_ENV_SIZE 0x2000
534 #define CONFIG_ENV_OFFSET 0x300000
535 #define CONFIG_ENV_SECT_SIZE 0x10000
537 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
538 #define CONFIG_ENV_SIZE 0x20000
539 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
542 #define CONFIG_MISC_INIT_R
544 #include <asm/fsl_secure_boot.h>
545 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */