2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1043AQDS_H__
8 #define __LS1043AQDS_H__
10 #include "ls1043a_common.h"
12 #define CONFIG_DISPLAY_CPUINFO
13 #define CONFIG_DISPLAY_BOARDINFO
15 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
16 #define CONFIG_SYS_TEXT_BASE 0x82000000
18 #define CONFIG_SYS_TEXT_BASE 0x60100000
22 unsigned long get_board_sys_clk(void);
23 unsigned long get_board_ddr_clk(void);
26 #define CONFIG_SYS_CLK_FREQ 100000000
27 #define CONFIG_DDR_CLK_FREQ 100000000
29 #define CONFIG_SKIP_LOWLEVEL_INIT
31 #define CONFIG_LAYERSCAPE_NS_ACCESS
33 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
34 /* Physical Memory Map */
35 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
36 #define CONFIG_NR_DRAM_BANKS 2
38 #define CONFIG_DDR_SPD
39 #define SPD_EEPROM_ADDRESS 0x51
40 #define CONFIG_SYS_SPD_BUS_NUM 0
42 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
43 #ifndef CONFIG_SYS_FSL_DDR4
44 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
47 #define CONFIG_DDR_ECC
49 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
50 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
53 #define CONFIG_SYS_HAS_SERDES
55 #ifdef CONFIG_SYS_DPAA_FMAN
56 #define CONFIG_FMAN_ENET
58 #define CONFIG_PHY_VITESSE
59 #define CONFIG_PHY_REALTEK
60 #define CONFIG_PHYLIB_10G
61 #define RGMII_PHY1_ADDR 0x1
62 #define RGMII_PHY2_ADDR 0x2
63 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
64 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
65 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
66 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
67 /* PHY address on QSGMII riser card on slot 1 */
68 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
69 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
70 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
71 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
72 /* PHY address on QSGMII riser card on slot 2 */
73 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
74 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
75 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
76 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
79 #ifdef CONFIG_RAMBOOT_PBL
80 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
83 #ifdef CONFIG_NAND_BOOT
84 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
88 #ifdef CONFIG_SD_BOOT_QSPI
89 #define CONFIG_SYS_FSL_PBL_RCW \
90 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
92 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
98 #define CONFIG_LPUART_32B_REG
102 #define CONFIG_LIBATA
103 #define CONFIG_SCSI_AHCI
104 #define CONFIG_SCSI_AHCI_PLAT
105 #define CONFIG_CMD_SCSI
106 #define CONFIG_CMD_FAT
107 #define CONFIG_CMD_EXT2
108 #define CONFIG_DOS_PARTITION
109 #define CONFIG_BOARD_LATE_INIT
111 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
113 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
114 #define CONFIG_SYS_SCSI_MAX_LUN 1
115 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
116 CONFIG_SYS_SCSI_MAX_LUN)
121 #ifndef CONFIG_SD_BOOT_QSPI
122 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
123 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
124 CSPR_PORT_SIZE_16 | \
127 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
128 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
130 CSPR_PORT_SIZE_16 | \
133 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
135 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
137 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
138 FTIM0_NOR_TEADC(0x5) | \
139 FTIM0_NOR_TEAHC(0x5))
140 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
141 FTIM1_NOR_TRAD_NOR(0x1a) | \
142 FTIM1_NOR_TSEQRAD_NOR(0x13))
143 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
144 FTIM2_NOR_TCH(0x4) | \
145 FTIM2_NOR_TWPH(0xe) | \
147 #define CONFIG_SYS_NOR_FTIM3 0
149 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
150 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
151 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
152 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
154 #define CONFIG_SYS_FLASH_EMPTY_INFO
155 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
156 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
158 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
159 #define CONFIG_SYS_WRITE_SWAPPED_DATA
162 * NAND Flash Definitions
164 #define CONFIG_NAND_FSL_IFC
166 #define CONFIG_SYS_NAND_BASE 0x7e800000
167 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
169 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
171 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
175 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
176 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
177 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
178 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
179 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
180 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
181 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
182 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
184 #define CONFIG_SYS_NAND_ONFI_DETECTION
186 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
187 FTIM0_NAND_TWP(0x18) | \
188 FTIM0_NAND_TWCHT(0x7) | \
190 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
191 FTIM1_NAND_TWBE(0x39) | \
192 FTIM1_NAND_TRR(0xe) | \
193 FTIM1_NAND_TRP(0x18))
194 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
195 FTIM2_NAND_TREH(0xa) | \
196 FTIM2_NAND_TWHRE(0x1e))
197 #define CONFIG_SYS_NAND_FTIM3 0x0
199 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
200 #define CONFIG_SYS_MAX_NAND_DEVICE 1
201 #define CONFIG_MTD_NAND_VERIFY_WRITE
202 #define CONFIG_CMD_NAND
204 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
207 #ifdef CONFIG_NAND_BOOT
208 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
209 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
210 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
213 #ifdef CONFIG_SD_BOOT_QSPI
214 #define CONFIG_QIXIS_I2C_ACCESS
215 #define CONFIG_SYS_NO_FLASH
216 #undef CONFIG_CMD_IMLS
222 #define CONFIG_FSL_QIXIS
224 #ifdef CONFIG_FSL_QIXIS
225 #define QIXIS_BASE 0x7fb00000
226 #define QIXIS_BASE_PHYS QIXIS_BASE
227 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
228 #define QIXIS_LBMAP_SWITCH 6
229 #define QIXIS_LBMAP_MASK 0x0f
230 #define QIXIS_LBMAP_SHIFT 0
231 #define QIXIS_LBMAP_DFLTBANK 0x00
232 #define QIXIS_LBMAP_ALTBANK 0x04
233 #define QIXIS_LBMAP_NAND 0x09
234 #define QIXIS_LBMAP_SD 0x00
235 #define QIXIS_LBMAP_SD_QSPI 0xff
236 #define QIXIS_RCW_SRC_NAND 0x106
237 #define QIXIS_RCW_SRC_SD 0x040
238 #define QIXIS_RST_CTL_RESET 0x41
239 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
240 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
241 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
243 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
244 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
248 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
249 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
250 CSOR_NOR_NOR_MODE_AVD_NOR | \
254 * QIXIS Timing parameters for IFC GPCM
256 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
257 FTIM0_GPCM_TEADC(0x20) | \
258 FTIM0_GPCM_TEAHC(0x10))
259 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
260 FTIM1_GPCM_TRAD(0x1f))
261 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
262 FTIM2_GPCM_TCH(0x8) | \
263 FTIM2_GPCM_TWP(0xf0))
264 #define CONFIG_SYS_FPGA_FTIM3 0x0
267 #ifdef CONFIG_NAND_BOOT
268 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
269 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
270 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
271 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
272 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
273 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
274 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
275 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
276 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
277 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
278 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
279 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
280 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
281 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
282 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
283 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
284 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
285 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
286 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
287 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
288 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
289 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
290 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
291 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
292 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
293 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
294 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
295 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
296 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
297 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
298 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
299 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
301 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
302 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
303 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
304 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
305 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
306 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
307 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
308 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
309 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
310 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
311 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
312 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
313 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
314 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
315 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
316 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
317 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
318 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
319 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
320 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
321 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
322 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
323 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
324 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
325 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
326 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
327 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
328 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
329 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
330 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
331 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
332 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
336 * I2C bus multiplexer
338 #define I2C_MUX_PCA_ADDR_PRI 0x77
339 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
340 #define I2C_RETIMER_ADDR 0x18
341 #define I2C_MUX_CH_DEFAULT 0x8
342 #define I2C_MUX_CH_CH7301 0xC
343 #define I2C_MUX_CH5 0xD
344 #define I2C_MUX_CH7 0xF
346 #define I2C_MUX_CH_VOL_MONITOR 0xa
348 /* Voltage monitor on channel 2*/
349 #define I2C_VOL_MONITOR_ADDR 0x40
350 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
351 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
352 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
354 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
355 #ifndef CONFIG_SPL_BUILD
358 #define CONFIG_VOL_MONITOR_IR36021_SET
359 #define CONFIG_VOL_MONITOR_INA220
360 /* The lowest and highest voltage allowed for LS1043AQDS */
361 #define VDD_MV_MIN 819
362 #define VDD_MV_MAX 1212
365 #ifdef CONFIG_SD_BOOT_QSPI
366 #define CONFIG_FSL_QSPI
367 #ifdef CONFIG_FSL_QSPI
368 #define CONFIG_SPI_FLASH_SPANSION
369 #define FSL_QSPI_FLASH_SIZE (1 << 24)
370 #define FSL_QSPI_FLASH_NUM 2
375 * Miscellaneous configurable options
377 #define CONFIG_MISC_INIT_R
378 #define CONFIG_SYS_LONGHELP /* undef to save memory */
379 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
380 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
381 #define CONFIG_SYS_PROMPT "=> "
382 #define CONFIG_AUTO_COMPLETE
383 #define CONFIG_SYS_PBSIZE \
384 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
385 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
387 #define CONFIG_CMD_GREPENV
388 #define CONFIG_CMD_MEMINFO
389 #define CONFIG_CMD_MEMTEST
390 #define CONFIG_SYS_MEMTEST_START 0x80000000
391 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
393 #define CONFIG_SYS_HZ 1000
397 * The stack sizes are set up in start.S using the settings below
399 #define CONFIG_STACKSIZE (30 * 1024)
401 #define CONFIG_SYS_INIT_SP_OFFSET \
402 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
404 #ifdef CONFIG_SPL_BUILD
405 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
407 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
413 #define CONFIG_ENV_OVERWRITE
415 #ifdef CONFIG_NAND_BOOT
416 #define CONFIG_ENV_IS_IN_NAND
417 #define CONFIG_ENV_SIZE 0x2000
418 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
419 #elif defined(CONFIG_SD_BOOT)
420 #define CONFIG_ENV_OFFSET (1024 * 1024)
421 #define CONFIG_ENV_IS_IN_MMC
422 #define CONFIG_SYS_MMC_ENV_DEV 0
423 #define CONFIG_ENV_SIZE 0x2000
425 #define CONFIG_ENV_IS_IN_FLASH
426 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
427 #define CONFIG_ENV_SECT_SIZE 0x20000
428 #define CONFIG_ENV_SIZE 0x20000
431 #define CONFIG_OF_LIBFDT
432 #define CONFIG_OF_BOARD_SETUP
433 #define CONFIG_CMD_BOOTZ
434 #define CONFIG_CMD_MII
435 #define CONFIG_CMDLINE_TAG
437 #include <asm/fsl_secure_boot.h>
439 #endif /* __LS1043AQDS_H__ */