2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1043AQDS_H__
8 #define __LS1043AQDS_H__
10 #include "ls1043a_common.h"
12 #define CONFIG_DISPLAY_BOARDINFO
14 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
15 #define CONFIG_SYS_TEXT_BASE 0x82000000
16 #elif defined(CONFIG_QSPI_BOOT)
17 #define CONFIG_SYS_TEXT_BASE 0x40010000
19 #define CONFIG_SYS_TEXT_BASE 0x60100000
23 unsigned long get_board_sys_clk(void);
24 unsigned long get_board_ddr_clk(void);
27 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
28 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
30 #define CONFIG_SKIP_LOWLEVEL_INIT
32 #define CONFIG_LAYERSCAPE_NS_ACCESS
34 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
35 /* Physical Memory Map */
36 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
37 #define CONFIG_NR_DRAM_BANKS 2
39 #define CONFIG_DDR_SPD
40 #define SPD_EEPROM_ADDRESS 0x51
41 #define CONFIG_SYS_SPD_BUS_NUM 0
43 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
44 #ifndef CONFIG_SYS_FSL_DDR4
45 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
48 #define CONFIG_DDR_ECC
50 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
51 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
54 #define CONFIG_SYS_HAS_SERDES
56 #ifdef CONFIG_SYS_DPAA_FMAN
57 #define CONFIG_FMAN_ENET
59 #define CONFIG_PHY_VITESSE
60 #define CONFIG_PHY_REALTEK
61 #define CONFIG_PHYLIB_10G
62 #define RGMII_PHY1_ADDR 0x1
63 #define RGMII_PHY2_ADDR 0x2
64 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
65 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
66 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
67 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
68 /* PHY address on QSGMII riser card on slot 1 */
69 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
70 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
71 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
72 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
73 /* PHY address on QSGMII riser card on slot 2 */
74 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
75 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
76 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
77 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
80 #ifdef CONFIG_RAMBOOT_PBL
81 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
84 #ifdef CONFIG_NAND_BOOT
85 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
89 #ifdef CONFIG_SD_BOOT_QSPI
90 #define CONFIG_SYS_FSL_PBL_RCW \
91 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
93 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
99 #define CONFIG_LPUART_32B_REG
103 #define CONFIG_LIBATA
104 #define CONFIG_SCSI_AHCI
105 #define CONFIG_SCSI_AHCI_PLAT
107 #define CONFIG_DOS_PARTITION
108 #define CONFIG_BOARD_LATE_INIT
111 #define CONFIG_ID_EEPROM
112 #define CONFIG_SYS_I2C_EEPROM_NXID
113 #define CONFIG_SYS_EEPROM_BUS_NUM 0
114 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
115 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
116 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
117 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
119 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
121 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
122 #define CONFIG_SYS_SCSI_MAX_LUN 1
123 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
124 CONFIG_SYS_SCSI_MAX_LUN)
129 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
130 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
131 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
132 CSPR_PORT_SIZE_16 | \
135 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
136 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
138 CSPR_PORT_SIZE_16 | \
141 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
143 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
145 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
146 FTIM0_NOR_TEADC(0x5) | \
147 FTIM0_NOR_TEAHC(0x5))
148 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
149 FTIM1_NOR_TRAD_NOR(0x1a) | \
150 FTIM1_NOR_TSEQRAD_NOR(0x13))
151 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
152 FTIM2_NOR_TCH(0x4) | \
153 FTIM2_NOR_TWPH(0xe) | \
155 #define CONFIG_SYS_NOR_FTIM3 0
157 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
158 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
159 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
160 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
162 #define CONFIG_SYS_FLASH_EMPTY_INFO
163 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
164 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
166 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
167 #define CONFIG_SYS_WRITE_SWAPPED_DATA
170 * NAND Flash Definitions
172 #define CONFIG_NAND_FSL_IFC
174 #define CONFIG_SYS_NAND_BASE 0x7e800000
175 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
177 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
179 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
183 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
184 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
185 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
186 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
187 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
188 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
189 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
190 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
192 #define CONFIG_SYS_NAND_ONFI_DETECTION
194 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
195 FTIM0_NAND_TWP(0x18) | \
196 FTIM0_NAND_TWCHT(0x7) | \
198 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
199 FTIM1_NAND_TWBE(0x39) | \
200 FTIM1_NAND_TRR(0xe) | \
201 FTIM1_NAND_TRP(0x18))
202 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
203 FTIM2_NAND_TREH(0xa) | \
204 FTIM2_NAND_TWHRE(0x1e))
205 #define CONFIG_SYS_NAND_FTIM3 0x0
207 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
208 #define CONFIG_SYS_MAX_NAND_DEVICE 1
209 #define CONFIG_MTD_NAND_VERIFY_WRITE
210 #define CONFIG_CMD_NAND
212 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
215 #ifdef CONFIG_NAND_BOOT
216 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
217 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
218 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
221 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
222 #define CONFIG_QIXIS_I2C_ACCESS
223 #define CONFIG_SYS_I2C_EARLY_INIT
224 #define CONFIG_SYS_NO_FLASH
230 #define CONFIG_FSL_QIXIS
232 #ifdef CONFIG_FSL_QIXIS
233 #define QIXIS_BASE 0x7fb00000
234 #define QIXIS_BASE_PHYS QIXIS_BASE
235 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
236 #define QIXIS_LBMAP_SWITCH 6
237 #define QIXIS_LBMAP_MASK 0x0f
238 #define QIXIS_LBMAP_SHIFT 0
239 #define QIXIS_LBMAP_DFLTBANK 0x00
240 #define QIXIS_LBMAP_ALTBANK 0x04
241 #define QIXIS_LBMAP_NAND 0x09
242 #define QIXIS_LBMAP_SD 0x00
243 #define QIXIS_LBMAP_SD_QSPI 0xff
244 #define QIXIS_LBMAP_QSPI 0xff
245 #define QIXIS_RCW_SRC_NAND 0x106
246 #define QIXIS_RCW_SRC_SD 0x040
247 #define QIXIS_RCW_SRC_QSPI 0x045
248 #define QIXIS_RST_CTL_RESET 0x41
249 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
250 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
251 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
253 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
254 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
258 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
259 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
260 CSOR_NOR_NOR_MODE_AVD_NOR | \
264 * QIXIS Timing parameters for IFC GPCM
266 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
267 FTIM0_GPCM_TEADC(0x20) | \
268 FTIM0_GPCM_TEAHC(0x10))
269 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
270 FTIM1_GPCM_TRAD(0x1f))
271 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
272 FTIM2_GPCM_TCH(0x8) | \
273 FTIM2_GPCM_TWP(0xf0))
274 #define CONFIG_SYS_FPGA_FTIM3 0x0
277 #ifdef CONFIG_NAND_BOOT
278 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
279 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
280 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
281 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
282 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
283 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
284 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
285 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
286 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
287 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
288 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
289 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
290 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
291 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
292 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
293 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
294 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
295 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
296 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
297 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
298 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
299 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
300 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
301 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
302 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
303 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
304 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
305 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
306 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
307 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
308 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
309 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
311 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
312 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
313 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
314 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
315 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
316 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
317 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
318 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
319 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
320 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
321 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
322 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
323 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
324 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
325 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
326 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
327 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
328 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
329 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
330 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
331 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
332 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
333 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
334 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
335 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
336 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
337 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
338 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
339 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
340 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
341 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
342 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
346 * I2C bus multiplexer
348 #define I2C_MUX_PCA_ADDR_PRI 0x77
349 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
350 #define I2C_RETIMER_ADDR 0x18
351 #define I2C_MUX_CH_DEFAULT 0x8
352 #define I2C_MUX_CH_CH7301 0xC
353 #define I2C_MUX_CH5 0xD
354 #define I2C_MUX_CH7 0xF
356 #define I2C_MUX_CH_VOL_MONITOR 0xa
358 /* Voltage monitor on channel 2*/
359 #define I2C_VOL_MONITOR_ADDR 0x40
360 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
361 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
362 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
364 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
365 #ifndef CONFIG_SPL_BUILD
368 #define CONFIG_VOL_MONITOR_IR36021_SET
369 #define CONFIG_VOL_MONITOR_INA220
370 /* The lowest and highest voltage allowed for LS1043AQDS */
371 #define VDD_MV_MIN 819
372 #define VDD_MV_MAX 1212
375 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
376 #define CONFIG_FSL_QSPI
377 #ifdef CONFIG_FSL_QSPI
378 #define CONFIG_SPI_FLASH_SPANSION
379 #define FSL_QSPI_FLASH_SIZE (1 << 24)
380 #define FSL_QSPI_FLASH_NUM 2
385 #define CONFIG_HAS_FSL_XHCI_USB
386 #ifdef CONFIG_HAS_FSL_XHCI_USB
387 #define CONFIG_USB_XHCI_FSL
388 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
389 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
393 * Miscellaneous configurable options
395 #define CONFIG_MISC_INIT_R
396 #define CONFIG_SYS_LONGHELP /* undef to save memory */
397 #define CONFIG_AUTO_COMPLETE
398 #define CONFIG_SYS_PBSIZE \
399 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
400 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
402 #define CONFIG_SYS_MEMTEST_START 0x80000000
403 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
405 #define CONFIG_SYS_HZ 1000
409 * The stack sizes are set up in start.S using the settings below
411 #define CONFIG_STACKSIZE (30 * 1024)
413 #define CONFIG_SYS_INIT_SP_OFFSET \
414 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
416 #ifdef CONFIG_SPL_BUILD
417 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
419 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
425 #define CONFIG_ENV_OVERWRITE
427 #ifdef CONFIG_NAND_BOOT
428 #define CONFIG_ENV_IS_IN_NAND
429 #define CONFIG_ENV_SIZE 0x2000
430 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
431 #elif defined(CONFIG_SD_BOOT)
432 #define CONFIG_ENV_OFFSET (1024 * 1024)
433 #define CONFIG_ENV_IS_IN_MMC
434 #define CONFIG_SYS_MMC_ENV_DEV 0
435 #define CONFIG_ENV_SIZE 0x2000
436 #elif defined(CONFIG_QSPI_BOOT)
437 #define CONFIG_ENV_IS_IN_SPI_FLASH
438 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
439 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
440 #define CONFIG_ENV_SECT_SIZE 0x10000
442 #define CONFIG_ENV_IS_IN_FLASH
443 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
444 #define CONFIG_ENV_SECT_SIZE 0x20000
445 #define CONFIG_ENV_SIZE 0x20000
448 #define CONFIG_CMDLINE_TAG
450 #include <asm/fsl_secure_boot.h>
452 #endif /* __LS1043AQDS_H__ */