2 * Copyright 2016 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1046A_COMMON_H
8 #define __LS1046A_COMMON_H
11 #ifdef CONFIG_SPL_BUILD
20 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
23 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
27 #define CONFIG_REMAKE_ELF
28 #define CONFIG_FSL_LAYERSCAPE
32 #include <asm/arch/config.h>
33 #include <asm/arch/stream_id_lsch2.h>
35 /* Link Definitions */
36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
38 #define CONFIG_SUPPORT_RAW_INITRD
40 #define CONFIG_SKIP_LOWLEVEL_INIT
42 #define CONFIG_VERY_BIG_RAM
43 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
44 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
46 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
48 #define CPU_RELEASE_ADDR secondary_boot_func
50 /* Generic Timer Definitions */
51 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
53 /* Size of malloc() pool */
54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
57 #define CONFIG_CONS_INDEX 1
58 #define CONFIG_SYS_NS16550_SERIAL
59 #define CONFIG_SYS_NS16550_REG_SIZE 1
60 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
62 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
66 #define CONFIG_SPL_FRAMEWORK
67 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
68 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
69 #define CONFIG_SPL_LIBCOMMON_SUPPORT
70 #define CONFIG_SPL_LIBGENERIC_SUPPORT
71 #define CONFIG_SPL_ENV_SUPPORT
72 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
73 #define CONFIG_SPL_WATCHDOG_SUPPORT
74 #define CONFIG_SPL_I2C_SUPPORT
75 #define CONFIG_SPL_SERIAL_SUPPORT
76 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
78 #define CONFIG_SPL_MMC_SUPPORT
79 #define CONFIG_SPL_TEXT_BASE 0x10000000
80 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
81 #define CONFIG_SPL_STACK 0x10020000
82 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
83 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
84 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
85 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
86 CONFIG_SPL_BSS_MAX_SIZE)
87 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
89 #ifdef CONFIG_SECURE_BOOT
90 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
92 * HDR would be appended at end of image and copied to DDR along
93 * with U-Boot image. Here u-boot max. size is 512K. So if binary
94 * size increases then increase this size in case of secure boot as
95 * it uses raw u-boot image instead of fit image.
97 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
99 #define CONFIG_SYS_MONITOR_LEN 0x100000
100 #endif /* ifdef CONFIG_SECURE_BOOT */
104 #ifdef CONFIG_NAND_BOOT
105 #define CONFIG_SPL_PBL_PAD
106 #define CONFIG_SPL_FRAMEWORK
107 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
108 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
109 #define CONFIG_SPL_LIBCOMMON_SUPPORT
110 #define CONFIG_SPL_LIBGENERIC_SUPPORT
111 #define CONFIG_SPL_ENV_SUPPORT
112 #define CONFIG_SPL_WATCHDOG_SUPPORT
113 #define CONFIG_SPL_I2C_SUPPORT
114 #define CONFIG_SPL_SERIAL_SUPPORT
115 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
117 #define CONFIG_SPL_NAND_SUPPORT
118 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
119 #define CONFIG_SPL_TEXT_BASE 0x10000000
120 #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
121 #define CONFIG_SPL_STACK 0x1001f000
122 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
123 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
125 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
126 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
127 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
128 CONFIG_SPL_BSS_MAX_SIZE)
129 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
130 #define CONFIG_SYS_MONITOR_LEN 0xa0000
134 #define CONFIG_SYS_I2C
135 #define CONFIG_SYS_I2C_MXC
136 #define CONFIG_SYS_I2C_MXC_I2C1
137 #define CONFIG_SYS_I2C_MXC_I2C2
138 #define CONFIG_SYS_I2C_MXC_I2C3
139 #define CONFIG_SYS_I2C_MXC_I2C4
142 #define CONFIG_PCIE1 /* PCIE controller 1 */
143 #define CONFIG_PCIE2 /* PCIE controller 2 */
144 #define CONFIG_PCIE3 /* PCIE controller 3 */
147 #define CONFIG_PCI_SCAN_SHOW
148 #define CONFIG_CMD_PCI
151 /* Command line configuration */
156 #define CONFIG_FSL_ESDHC
157 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
162 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
167 #define CONFIG_SYS_DPAA_FMAN
168 #ifdef CONFIG_SYS_DPAA_FMAN
169 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
172 #ifdef CONFIG_SD_BOOT
174 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
175 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
176 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
178 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
179 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
180 #elif defined(CONFIG_QSPI_BOOT)
181 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
182 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
183 #define CONFIG_ENV_SPI_BUS 0
184 #define CONFIG_ENV_SPI_CS 0
185 #define CONFIG_ENV_SPI_MAX_HZ 1000000
186 #define CONFIG_ENV_SPI_MODE 0x03
187 #elif defined(CONFIG_NAND_BOOT)
188 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
189 #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
191 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
192 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
194 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
195 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
198 /* Miscellaneous configurable options */
199 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
201 #define CONFIG_HWCONFIG
202 #define HWCONFIG_BUFFER_SIZE 128
204 #include <config_distro_defaults.h>
205 #ifndef CONFIG_SPL_BUILD
206 #define BOOT_TARGET_DEVICES(func) \
209 #include <config_distro_bootcmd.h>
213 /* Initial environment variables */
214 #define CONFIG_EXTRA_ENV_SETTINGS \
215 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
216 "ramdisk_addr=0x800000\0" \
217 "ramdisk_size=0x2000000\0" \
218 "fdt_high=0xffffffffffffffff\0" \
219 "initrd_high=0xffffffffffffffff\0" \
220 "fdt_addr=0x64f00000\0" \
221 "kernel_addr=0x65000000\0" \
222 "scriptaddr=0x80000000\0" \
223 "scripthdraddr=0x80080000\0" \
224 "fdtheader_addr_r=0x80100000\0" \
225 "kernelheader_addr_r=0x80200000\0" \
226 "load_addr=0xa0000000\0" \
227 "kernel_addr_r=0x81000000\0" \
228 "fdt_addr_r=0x90000000\0" \
229 "ramdisk_addr_r=0xa0000000\0" \
230 "kernel_start=0x1000000\0" \
231 "kernel_load=0xa0000000\0" \
232 "kernel_size=0x2800000\0" \
233 "console=ttyS0,115200\0" \
234 MTDPARTS_DEFAULT "\0" \
236 "boot_scripts=ls1046ardb_boot.scr\0" \
237 "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \
238 "scan_dev_for_boot_part=" \
239 "part list ${devtype} ${devnum} devplist; " \
240 "env exists devplist || setenv devplist 1; " \
241 "for distro_bootpart in ${devplist}; do " \
242 "if fstype ${devtype} " \
243 "${devnum}:${distro_bootpart} " \
244 "bootfstype; then " \
245 "run scan_dev_for_boot; " \
248 "scan_dev_for_boot=" \
249 "echo Scanning ${devtype} " \
250 "${devnum}:${distro_bootpart}...; " \
251 "for prefix in ${boot_prefixes}; do " \
252 "run scan_dev_for_scripts; " \
256 "load ${devtype} ${devnum}:${distro_bootpart} " \
257 "${scriptaddr} ${prefix}${script}; " \
258 "env exists secureboot && load ${devtype} " \
259 "${devnum}:${distro_bootpart} " \
260 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
261 "&& esbc_validate ${scripthdraddr};" \
262 "source ${scriptaddr}\0" \
263 "installer=load mmc 0:2 $load_addr " \
264 "/flex_installer_arm64.itb; " \
265 "bootm $load_addr#ls1046ardb\0" \
266 "qspi_bootcmd=echo Trying load from qspi..;" \
267 "sf probe && sf read $load_addr " \
268 "$kernel_start $kernel_size && bootm $load_addr#$board\0"
271 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
272 "earlycon=uart8250,mmio,0x21c0500 " \
276 /* Monitor Command Prompt */
277 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
278 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
279 sizeof(CONFIG_SYS_PROMPT) + 16)
280 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
281 #define CONFIG_SYS_LONGHELP
283 #define CONFIG_AUTO_COMPLETE
284 #define CONFIG_SYS_MAXARGS 64 /* max command args */
286 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
288 #include <asm/arch/soc.h>
290 #endif /* __LS1046A_COMMON_H */