4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1088_COMMON_H
8 #define __LS1088_COMMON_H
11 #define CONFIG_REMAKE_ELF
12 #define CONFIG_FSL_LAYERSCAPE
15 #include <asm/arch/stream_id_lsch3.h>
16 #include <asm/arch/config.h>
17 #include <asm/arch/soc.h>
19 /* Link Definitions */
20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
22 /* Link Definitions */
23 #ifdef CONFIG_QSPI_BOOT
24 #define CONFIG_SYS_TEXT_BASE 0x20100000
26 #define CONFIG_SYS_TEXT_BASE 0x30100000
29 #define CONFIG_SUPPORT_RAW_INITRD
32 #define CONFIG_SKIP_LOWLEVEL_INIT
34 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
36 #define CONFIG_VERY_BIG_RAM
37 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
38 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
39 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
40 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
41 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
45 #define CPU_RELEASE_ADDR secondary_boot_func
48 #define CONFIG_CMD_PCI
51 /* Size of malloc() pool */
52 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
55 #define CONFIG_SYS_I2C
56 #define CONFIG_SYS_I2C_MXC
57 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
58 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
59 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
60 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
63 #define CONFIG_CONS_INDEX 1
64 #define CONFIG_SYS_NS16550_SERIAL
65 #define CONFIG_SYS_NS16550_REG_SIZE 1
66 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
68 #define CONFIG_BAUDRATE 115200
69 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
72 #define CONFIG_FSL_IFC
75 * During booting, IFC is mapped at the region of 0x30000000.
76 * But this region is limited to 256MB. To accommodate NOR, promjet
77 * and FPGA. This region is divided as below:
78 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
79 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
80 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
82 * To accommodate bigger NOR flash and other devices, we will map IFC
83 * chip selects to as below:
84 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
85 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
86 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
87 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
88 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
90 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
91 * CONFIG_SYS_FLASH_BASE has the final address (core view)
92 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
93 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
94 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
97 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
98 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
99 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
101 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
102 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
105 unsigned long long get_qixis_addr(void);
108 #define QIXIS_BASE get_qixis_addr()
109 #define QIXIS_BASE_PHYS 0x20000000
110 #define QIXIS_BASE_PHYS_EARLY 0xC000000
113 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
114 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
118 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
119 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
120 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
121 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
122 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
123 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
124 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
126 /* Define phy_reset function to boot the MC based on mcinitcmd.
127 * This happens late enough to properly fixup u-boot env MAC addresses.
129 #define CONFIG_RESET_PHY_R
132 * Carve out a DDR region which will not be used by u-boot/Linux
134 * It will be used by MC and Debug Server. The MC region must be
135 * 512MB aligned, so the min size to hide is 512MB.
138 #if defined(CONFIG_FSL_MC_ENET)
139 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
142 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
144 /* Command line configuration */
145 #define CONFIG_CMD_GREPENV
146 #define CONFIG_CMD_CACHE
148 /* Miscellaneous configurable options */
149 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
151 /* Physical Memory Map */
152 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
154 #define CONFIG_NR_DRAM_BANKS 2
156 #define CONFIG_HWCONFIG
157 #define HWCONFIG_BUFFER_SIZE 128
159 /* #define CONFIG_DISPLAY_CPUINFO */
161 /* Allow to overwrite serial and ethaddr */
162 #define CONFIG_ENV_OVERWRITE
164 /* Initial environment variables */
165 #define CONFIG_EXTRA_ENV_SETTINGS \
166 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
167 "loadaddr=0x80100000\0" \
168 "kernel_addr=0x100000\0" \
169 "ramdisk_addr=0x800000\0" \
170 "ramdisk_size=0x2000000\0" \
171 "fdt_high=0xa0000000\0" \
172 "initrd_high=0xffffffffffffffff\0" \
173 "kernel_start=0x581000000\0" \
174 "kernel_load=0xa0000000\0" \
175 "kernel_size=0x2800000\0" \
176 "console=ttyAMA0,38400n8\0" \
177 "mcinitcmd=fsl_mc start mc 0x580a00000" \
180 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
181 "earlycon=uart8250,mmio,0x21c0500 " \
182 "ramdisk_size=0x3000000 default_hugepagesz=2m" \
183 " hugepagesz=2m hugepages=256"
184 #if defined(CONFIG_QSPI_BOOT)
185 #define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
186 "sf read 0x80200000 0xd00000 0x100000;"\
187 " fsl_mc apply dpl 0x80200000 &&" \
188 " sf read $kernel_load $kernel_start" \
189 " $kernel_size && bootm $kernel_load"
191 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
192 " cp.b $kernel_start $kernel_load" \
193 " $kernel_size && bootm $kernel_load"
196 /* Monitor Command Prompt */
197 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
198 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
199 sizeof(CONFIG_SYS_PROMPT) + 16)
200 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
201 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
202 #define CONFIG_SYS_LONGHELP
203 #define CONFIG_CMDLINE_EDITING 1
204 #define CONFIG_AUTO_COMPLETE
205 #define CONFIG_SYS_MAXARGS 64 /* max command args */
207 #define CONFIG_PANIC_HANG /* do not reset board on panic */
209 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
211 #endif /* __LS1088_COMMON_H */