2 * Copyright (C) 2014 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_REMAKE_ELF
11 #define CONFIG_FSL_LAYERSCAPE
12 #define CONFIG_FSL_LSCH3
15 #define CONFIG_FSL_TZPC_BP147
17 #include <asm/arch/ls2080a_stream_id.h>
18 #include <asm/arch/config.h>
19 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
20 #define CONFIG_SYS_HAS_SERDES
23 /* Link Definitions */
24 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
26 /* We need architecture specific misc initializations */
27 #define CONFIG_ARCH_MISC_INIT
29 /* Link Definitions */
31 #define CONFIG_SYS_TEXT_BASE 0x80400000
33 #define CONFIG_SYS_TEXT_BASE 0x30100000
37 #define CONFIG_SYS_NO_FLASH
40 #define CONFIG_SUPPORT_RAW_INITRD
42 #define CONFIG_SKIP_LOWLEVEL_INIT
43 #define CONFIG_BOARD_EARLY_INIT_F 1
46 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
48 #ifndef CONFIG_SYS_FSL_DDR4
49 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
50 #define CONFIG_SYS_DDR_RAW_TIMING
53 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
55 #define CONFIG_VERY_BIG_RAM
56 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
57 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
58 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
59 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
60 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
65 #define CPU_RELEASE_ADDR secondary_boot_func
67 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
68 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
69 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
71 * DDR controller use 0 as the base address for binding.
72 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
74 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
75 #define CONFIG_DP_DDR_CTRL 2
76 #define CONFIG_DP_DDR_NUM_CTRLS 1
79 /* Generic Timer Definitions */
81 * This is not an accurate number. It is used in start.S. The frequency
82 * will be udpated later when get_bus_freq(0) is available.
84 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
86 /* Size of malloc() pool */
87 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
90 #define CONFIG_SYS_I2C
91 #define CONFIG_SYS_I2C_MXC
92 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
93 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
94 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
95 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
98 #define CONFIG_CONS_INDEX 1
99 #define CONFIG_SYS_NS16550_SERIAL
100 #define CONFIG_SYS_NS16550_REG_SIZE 1
101 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
103 #define CONFIG_BAUDRATE 115200
104 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
107 #define CONFIG_FSL_IFC
110 * During booting, IFC is mapped at the region of 0x30000000.
111 * But this region is limited to 256MB. To accommodate NOR, promjet
112 * and FPGA. This region is divided as below:
113 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
114 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
115 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
117 * To accommodate bigger NOR flash and other devices, we will map IFC
118 * chip selects to as below:
119 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
120 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
121 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
122 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
123 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
125 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
126 * CONFIG_SYS_FLASH_BASE has the final address (core view)
127 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
128 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
129 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
132 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
133 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
134 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
136 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
137 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
139 #ifndef CONFIG_SYS_NO_FLASH
140 #define CONFIG_FLASH_CFI_DRIVER
141 #define CONFIG_SYS_FLASH_CFI
142 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
143 #define CONFIG_SYS_FLASH_QUIET_TEST
147 unsigned long long get_qixis_addr(void);
149 #define QIXIS_BASE get_qixis_addr()
150 #define QIXIS_BASE_PHYS 0x20000000
151 #define QIXIS_BASE_PHYS_EARLY 0xC000000
152 #define QIXIS_STAT_PRES1 0xb
153 #define QIXIS_SDID_MASK 0x07
154 #define QIXIS_ESDHC_NO_ADAPTER 0x7
156 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
157 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
159 /* Debug Server firmware */
160 #define CONFIG_FSL_DEBUG_SERVER
162 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
165 #define CONFIG_FSL_MC_ENET
166 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
167 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
168 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
169 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
170 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
172 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
173 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
176 * Carve out a DDR region which will not be used by u-boot/Linux
178 * It will be used by MC and Debug Server. The MC region must be
179 * 512MB aligned, so the min size to hide is 512MB.
181 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
182 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024)
183 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
184 #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024)
188 #define CONFIG_PCIE1 /* PCIE controller 1 */
189 #define CONFIG_PCIE2 /* PCIE controller 2 */
190 #define CONFIG_PCIE3 /* PCIE controller 3 */
191 #define CONFIG_PCIE4 /* PCIE controller 4 */
192 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
193 #ifdef CONFIG_LS2080A
194 #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
197 #define CONFIG_SYS_PCI_64BIT
199 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
200 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
201 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
202 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
204 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
205 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
206 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
208 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
209 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
210 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
212 /* Command line configuration */
213 #define CONFIG_CMD_ENV
215 /* Miscellaneous configurable options */
216 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
217 #define CONFIG_ARCH_EARLY_INIT_R
219 /* Physical Memory Map */
220 /* fixme: these need to be checked against the board */
221 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
223 #define CONFIG_NR_DRAM_BANKS 3
225 #define CONFIG_HWCONFIG
226 #define HWCONFIG_BUFFER_SIZE 128
228 #define CONFIG_DISPLAY_CPUINFO
230 /* Allow to overwrite serial and ethaddr */
231 #define CONFIG_ENV_OVERWRITE
233 /* Initial environment variables */
234 #define CONFIG_EXTRA_ENV_SETTINGS \
235 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
236 "loadaddr=0x80100000\0" \
237 "kernel_addr=0x100000\0" \
238 "ramdisk_addr=0x800000\0" \
239 "ramdisk_size=0x2000000\0" \
240 "fdt_high=0xa0000000\0" \
241 "initrd_high=0xffffffffffffffff\0" \
242 "kernel_start=0x581200000\0" \
243 "kernel_load=0xa0000000\0" \
244 "kernel_size=0x2800000\0" \
245 "console=ttyAMA0,38400n8\0" \
246 "mcinitcmd=fsl_mc start mc 0x580300000" \
249 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
250 "earlycon=uart8250,mmio,0x21c0500 " \
251 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
252 " hugepagesz=2m hugepages=256"
253 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \
254 " cp.b $kernel_start $kernel_load" \
255 " $kernel_size && bootm $kernel_load"
256 #define CONFIG_BOOTDELAY 10
258 /* Monitor Command Prompt */
259 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
260 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
261 sizeof(CONFIG_SYS_PROMPT) + 16)
262 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
263 #define CONFIG_SYS_LONGHELP
264 #define CONFIG_CMDLINE_EDITING 1
265 #define CONFIG_AUTO_COMPLETE
266 #define CONFIG_SYS_MAXARGS 64 /* max command args */
268 #define CONFIG_PANIC_HANG /* do not reset board on panic */
270 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
271 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
272 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
273 #define CONFIG_SPL_ENV_SUPPORT
274 #define CONFIG_SPL_FRAMEWORK
275 #define CONFIG_SPL_I2C_SUPPORT
276 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
277 #define CONFIG_SPL_LIBCOMMON_SUPPORT
278 #define CONFIG_SPL_LIBGENERIC_SUPPORT
279 #define CONFIG_SPL_MAX_SIZE 0x16000
280 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
281 #define CONFIG_SPL_NAND_SUPPORT
282 #define CONFIG_SPL_SERIAL_SUPPORT
283 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
284 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
285 #define CONFIG_SPL_TEXT_BASE 0x1800a000
287 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
288 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
289 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
290 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
291 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
293 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
295 #endif /* __LS2_COMMON_H */