3 * Copyright 2015 Freescale Semiconductor
5 * SPDX-License-Identifier: GPL-2.0+
11 #include "ls2080a_common.h"
13 #undef CONFIG_CONS_INDEX
14 #define CONFIG_CONS_INDEX 2
16 #ifdef CONFIG_FSL_QSPI
17 #ifdef CONFIG_TARGET_LS2081ARDB
18 #define CONFIG_QIXIS_I2C_ACCESS
20 #define CONFIG_SYS_I2C_EARLY_INIT
23 #define I2C_MUX_CH_VOL_MONITOR 0xa
24 #define I2C_VOL_MONITOR_ADDR 0x38
25 #define CONFIG_VOL_MONITOR_IR36021_READ
26 #define CONFIG_VOL_MONITOR_IR36021_SET
28 #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
29 #ifndef CONFIG_SPL_BUILD
32 /* step the IR regulator in 5mV increments */
33 #define IR_VDD_STEP_DOWN 5
34 #define IR_VDD_STEP_UP 5
35 /* The lowest and highest voltage allowed for LS2080ARDB */
36 #define VDD_MV_MIN 819
37 #define VDD_MV_MAX 1212
40 unsigned long get_board_sys_clk(void);
43 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
44 #define CONFIG_DDR_CLK_FREQ 133333333
45 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
47 #define CONFIG_DDR_SPD
48 #define CONFIG_DDR_ECC
49 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
50 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
51 #define SPD_EEPROM_ADDRESS1 0x51
52 #define SPD_EEPROM_ADDRESS2 0x52
53 #define SPD_EEPROM_ADDRESS3 0x53
54 #define SPD_EEPROM_ADDRESS4 0x54
55 #define SPD_EEPROM_ADDRESS5 0x55
56 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
57 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
58 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
59 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
60 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
61 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
62 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
64 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
68 #define CONFIG_SCSI_AHCI
69 #define CONFIG_SCSI_AHCI_PLAT
71 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
72 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
74 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
75 #define CONFIG_SYS_SCSI_MAX_LUN 1
76 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
77 CONFIG_SYS_SCSI_MAX_LUN)
79 #ifndef CONFIG_FSL_QSPI
80 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
82 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
83 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
84 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
86 #define CONFIG_SYS_NOR0_CSPR \
87 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
91 #define CONFIG_SYS_NOR0_CSPR_EARLY \
92 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
96 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
97 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
98 FTIM0_NOR_TEADC(0x5) | \
100 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
101 FTIM1_NOR_TRAD_NOR(0x1a) |\
102 FTIM1_NOR_TSEQRAD_NOR(0x13))
103 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
104 FTIM2_NOR_TCH(0x4) | \
105 FTIM2_NOR_TWPH(0x0E) | \
107 #define CONFIG_SYS_NOR_FTIM3 0x04000000
108 #define CONFIG_SYS_IFC_CCR 0x01000000
110 #ifdef CONFIG_MTD_NOR_FLASH
111 #define CONFIG_FLASH_CFI_DRIVER
112 #define CONFIG_SYS_FLASH_CFI
113 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
114 #define CONFIG_SYS_FLASH_QUIET_TEST
115 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
117 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
118 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
119 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
120 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
122 #define CONFIG_SYS_FLASH_EMPTY_INFO
123 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
124 CONFIG_SYS_FLASH_BASE + 0x40000000}
127 #define CONFIG_NAND_FSL_IFC
128 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
129 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
131 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
132 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
133 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
134 | CSPR_MSEL_NAND /* MSEL = NAND */ \
136 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
138 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
139 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
140 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
141 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
142 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
143 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
144 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
146 #define CONFIG_SYS_NAND_ONFI_DETECTION
148 /* ONFI NAND Flash mode0 Timing Params */
149 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
150 FTIM0_NAND_TWP(0x30) | \
151 FTIM0_NAND_TWCHT(0x0e) | \
152 FTIM0_NAND_TWH(0x14))
153 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
154 FTIM1_NAND_TWBE(0xab) | \
155 FTIM1_NAND_TRR(0x1c) | \
156 FTIM1_NAND_TRP(0x30))
157 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
158 FTIM2_NAND_TREH(0x14) | \
159 FTIM2_NAND_TWHRE(0x3c))
160 #define CONFIG_SYS_NAND_FTIM3 0x0
162 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
163 #define CONFIG_SYS_MAX_NAND_DEVICE 1
164 #define CONFIG_MTD_NAND_VERIFY_WRITE
166 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
167 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
168 #define QIXIS_LBMAP_SWITCH 0x06
169 #define QIXIS_LBMAP_MASK 0x0f
170 #define QIXIS_LBMAP_SHIFT 0
171 #define QIXIS_LBMAP_DFLTBANK 0x00
172 #define QIXIS_LBMAP_ALTBANK 0x04
173 #define QIXIS_LBMAP_NAND 0x09
174 #define QIXIS_RST_CTL_RESET 0x31
175 #define QIXIS_RST_CTL_RESET_EN 0x30
176 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
177 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
178 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
179 #define QIXIS_RCW_SRC_NAND 0x119
180 #define QIXIS_RST_FORCE_MEM 0x01
182 #define CONFIG_SYS_CSPR3_EXT (0x0)
183 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
187 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
192 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
193 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
194 /* QIXIS Timing parameters for IFC CS3 */
195 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
196 FTIM0_GPCM_TEADC(0x0e) | \
197 FTIM0_GPCM_TEAHC(0x0e))
198 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
199 FTIM1_GPCM_TRAD(0x3f))
200 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
201 FTIM2_GPCM_TCH(0xf) | \
202 FTIM2_GPCM_TWP(0x3E))
203 #define CONFIG_SYS_CS3_FTIM3 0x0
205 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
206 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
207 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
208 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
209 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
210 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
211 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
212 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
213 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
214 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
215 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
216 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
217 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
218 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
219 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
220 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
221 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
222 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
224 #define CONFIG_ENV_OFFSET (2048 * 1024)
225 #define CONFIG_ENV_SECT_SIZE 0x20000
226 #define CONFIG_ENV_SIZE 0x2000
227 #define CONFIG_SPL_PAD_TO 0x80000
228 #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
229 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
231 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
232 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
233 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
234 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
235 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
236 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
237 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
238 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
239 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
240 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
241 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
242 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
243 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
244 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
245 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
246 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
247 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
249 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
250 #define CONFIG_ENV_SECT_SIZE 0x20000
251 #define CONFIG_ENV_SIZE 0x2000
254 /* Debug Server firmware */
255 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
256 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
258 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
260 #ifdef CONFIG_TARGET_LS2081ARDB
261 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
262 #define QIXIS_QMAP_MASK 0x07
263 #define QIXIS_QMAP_SHIFT 5
264 #define QIXIS_LBMAP_DFLTBANK 0x00
265 #define QIXIS_LBMAP_QSPI 0x00
266 #define QIXIS_RCW_SRC_QSPI 0x62
267 #define QIXIS_LBMAP_ALTBANK 0x20
268 #define QIXIS_RST_CTL_RESET 0x31
269 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
270 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
271 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
272 #define QIXIS_LBMAP_MASK 0x0f
273 #define QIXIS_RST_CTL_RESET_EN 0x30
279 #ifdef CONFIG_TARGET_LS2081ARDB
280 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
282 #define I2C_MUX_PCA_ADDR 0x75
283 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
285 /* I2C bus multiplexer */
286 #define I2C_MUX_CH_DEFAULT 0x8
289 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
290 #define CONFIG_SPI_FLASH
291 #ifdef CONFIG_FSL_DSPI
292 #define CONFIG_SPI_FLASH_STMICRO
294 #ifdef CONFIG_FSL_QSPI
295 #define CONFIG_SPI_FLASH_SPANSION
297 #define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */
298 #define FSL_QSPI_FLASH_NUM 2
305 #ifdef CONFIG_TARGET_LS2081ARDB
306 #define CONFIG_RTC_PCF8563 1
307 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
309 #define CONFIG_RTC_DS3231 1
310 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
314 #define CONFIG_ID_EEPROM
315 #define CONFIG_SYS_I2C_EEPROM_NXID
316 #define CONFIG_SYS_EEPROM_BUS_NUM 0
317 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
318 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
319 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
320 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
322 #define CONFIG_FSL_MEMAC
325 #define CONFIG_PCI_SCAN_SHOW
330 #define CONFIG_FSL_ESDHC
331 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
334 #define CONFIG_MISC_INIT_R
336 #undef CONFIG_CMDLINE_EDITING
337 #include <config_distro_defaults.h>
339 #define BOOT_TARGET_DEVICES(func) \
342 func(SCSI, scsi, 0) \
344 #include <config_distro_bootcmd.h>
346 #ifdef CONFIG_QSPI_BOOT
347 #define MC_INIT_CMD \
348 "mcinitcmd=env exists secureboot && " \
349 "esbc_validate 0x20700000 && " \
350 "esbc_validate 0x20740000;" \
351 "fsl_mc start mc 0x20a00000 0x20e00000 \0"
352 #elif defined(CONFIG_SD_BOOT)
353 #define MC_INIT_CMD \
354 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
355 "mmc read 0x80100000 0x7000 0x800;" \
356 "env exists secureboot && " \
357 "mmc read 0x80700000 0x3800 0x10 && " \
358 "mmc read 0x80740000 0x3A00 0x10 && " \
359 "esbc_validate 0x80700000 && " \
360 "esbc_validate 0x80740000 ;" \
361 "fsl_mc start mc 0x80000000 0x80100000\0" \
362 "mcmemsize=0x70000000\0"
364 #define MC_INIT_CMD \
365 "mcinitcmd=env exists secureboot && " \
366 "esbc_validate 0x580700000 && " \
367 "esbc_validate 0x580740000; " \
368 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
371 /* Initial environment variables */
372 #undef CONFIG_EXTRA_ENV_SETTINGS
373 #define CONFIG_EXTRA_ENV_SETTINGS \
374 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
375 "ramdisk_addr=0x800000\0" \
376 "ramdisk_size=0x2000000\0" \
377 "fdt_high=0xa0000000\0" \
378 "initrd_high=0xffffffffffffffff\0" \
379 "fdt_addr=0x64f00000\0" \
380 "kernel_addr=0x65000000\0" \
381 "kernel_start=0x1000000\0" \
382 "kernelheader_start=0x800000\0" \
383 "scriptaddr=0x80000000\0" \
384 "scripthdraddr=0x80080000\0" \
385 "fdtheader_addr_r=0x80100000\0" \
386 "kernelheader_addr_r=0x80200000\0" \
387 "kernelheader_addr=0x580800000\0" \
388 "kernel_addr_r=0x81000000\0" \
389 "kernelheader_size=0x40000\0" \
390 "fdt_addr_r=0x90000000\0" \
391 "load_addr=0xa0000000\0" \
392 "kernel_size=0x2800000\0" \
393 "kernel_addr_sd=0x8000\0" \
394 "kernel_size_sd=0x14000\0" \
395 "console=ttyAMA0,38400n8\0" \
396 "mcmemsize=0x70000000\0" \
397 "sd_bootcmd=echo Trying load from SD ..;" \
398 "mmcinfo; mmc read $load_addr " \
399 "$kernel_addr_sd $kernel_size_sd && " \
400 "bootm $load_addr#$board\0" \
403 "boot_scripts=ls2088ardb_boot.scr\0" \
404 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
405 "scan_dev_for_boot_part=" \
406 "part list ${devtype} ${devnum} devplist; " \
407 "env exists devplist || setenv devplist 1; " \
408 "for distro_bootpart in ${devplist}; do " \
409 "if fstype ${devtype} " \
410 "${devnum}:${distro_bootpart} " \
411 "bootfstype; then " \
412 "run scan_dev_for_boot; " \
415 "scan_dev_for_boot=" \
416 "echo Scanning ${devtype} " \
417 "${devnum}:${distro_bootpart}...; " \
418 "for prefix in ${boot_prefixes}; do " \
419 "run scan_dev_for_scripts; " \
422 "load ${devtype} ${devnum}:${distro_bootpart} " \
423 "${scriptaddr} ${prefix}${script}; " \
424 "env exists secureboot && load ${devtype} " \
425 "${devnum}:${distro_bootpart} " \
426 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
427 "&& esbc_validate ${scripthdraddr};" \
428 "source ${scriptaddr}\0" \
429 "qspi_bootcmd=echo Trying load from qspi..;" \
430 "sf probe && sf read $load_addr " \
431 "$kernel_start $kernel_size ; env exists secureboot &&" \
432 "sf read $kernelheader_addr_r $kernelheader_start " \
433 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
434 " bootm $load_addr#$board\0" \
435 "nor_bootcmd=echo Trying load from nor..;" \
436 "cp.b $kernel_addr $load_addr " \
437 "$kernel_size ; env exists secureboot && " \
438 "cp.b $kernelheader_addr $kernelheader_addr_r " \
439 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
440 "bootm $load_addr#$board\0"
442 #undef CONFIG_BOOTCOMMAND
443 #ifdef CONFIG_QSPI_BOOT
444 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
445 #define CONFIG_BOOTCOMMAND \
446 "env exists mcinitcmd && env exists secureboot "\
447 "&& esbc_validate 0x20780000; " \
448 "env exists mcinitcmd && " \
449 "fsl_mc lazyapply dpl 0x20d00000; " \
450 "run distro_bootcmd;env exists secureboot " \
451 " && esbc_halt;run qspi_bootcmd; "
452 #elif defined(CONFIG_SD_BOOT)
453 /* Try to boot an on-SD kernel first, then do normal distro boot */
454 #define CONFIG_BOOTCOMMAND \
455 "env exists mcinitcmd && env exists secureboot "\
456 "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
457 "&& esbc_validate $load_addr; " \
458 "env exists mcinitcmd && run mcinitcmd " \
459 "&& mmc read 0x88000000 0x6800 0x800 " \
460 "&& fsl_mc lazyapply dpl 0x88000000; " \
461 "run distro_bootcmd;env exists secureboot " \
462 "&& esbc_halt;run sd_bootcmd;"
464 /* Try to boot an on-NOR kernel first, then do normal distro boot */
465 #define CONFIG_BOOTCOMMAND \
466 "env exists mcinitcmd && env exists secureboot "\
467 "&& esbc_validate 0x580780000; env exists mcinitcmd "\
468 "&& fsl_mc lazyapply dpl 0x580d00000;" \
469 "run distro_bootcmd; env exists secureboot " \
470 "&& esbc_halt; run nor_bootcmd;"
473 /* MAC/PHY configuration */
474 #ifdef CONFIG_FSL_MC_ENET
475 #define CONFIG_PHYLIB_10G
476 #define CONFIG_PHY_AQUANTIA
477 #define CONFIG_PHY_CORTINA
478 #define CONFIG_SYS_CORTINA_FW_IN_NOR
479 #ifdef CONFIG_QSPI_BOOT
480 #define CONFIG_CORTINA_FW_ADDR 0x20980000
482 #define CONFIG_CORTINA_FW_ADDR 0x580980000
484 #define CONFIG_CORTINA_FW_LENGTH 0x40000
486 #define CORTINA_PHY_ADDR1 0x10
487 #define CORTINA_PHY_ADDR2 0x11
488 #define CORTINA_PHY_ADDR3 0x12
489 #define CORTINA_PHY_ADDR4 0x13
490 #define AQ_PHY_ADDR1 0x00
491 #define AQ_PHY_ADDR2 0x01
492 #define AQ_PHY_ADDR3 0x02
493 #define AQ_PHY_ADDR4 0x03
494 #define AQR405_IRQ_MASK 0x36
497 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
498 #define CONFIG_PHY_AQUANTIA
501 #include <asm/fsl_secure_boot.h>
503 #endif /* __LS2_RDB_H */