3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 /* External logbuffer support */
32 #define CONFIG_LOGBUFFER
35 * High Level Configuration Options
39 #define CONFIG_MPC823 1 /* This is a MPC823E CPU */
40 #define CONFIG_LWMON 1 /* ...on a LWMON board */
42 /* Default Ethernet MAC address */
43 #define CONFIG_ETHADDR 00:11:B0:00:00:00
45 /* The default Ethernet MAC address can be overwritten just once */
47 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
50 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
51 #define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
53 #define CONFIG_LCD 1 /* use LCD controller ... */
54 #define CONFIG_HLD1045 1 /* ... with a HLD1045 display */
56 #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
58 #define CONFIG_SERIAL_MULTI 1
59 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
60 #define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */
62 #define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */
64 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
66 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
68 /* pre-boot commands */
69 #define CONFIG_PREBOOT "setenv bootdelay 15"
71 #undef CONFIG_BOOTARGS
74 #define CONFIG_POST (CFG_POST_CACHE | \
89 * # = 0x28 = ENTER : enable bootmessages on LCD
90 * 2 = 0x3A+0x3C = F1 + F3 : enable update mode
91 * 3 = 0x3C+0x3F = F3 + F6 : enable test mode
94 #define CONFIG_BOOTCOMMAND "autoscr 40040000;saveenv"
96 /* "gatewayip=10.8.211.250\0" \ */
97 #define CONFIG_EXTRA_ENV_SETTINGS \
98 "kernel_addr=40080000\0" \
99 "ramdisk_addr=40280000\0" \
100 "netmask=255.255.192.0\0" \
101 "serverip=10.8.2.101\0" \
102 "ipaddr=10.8.57.0\0" \
105 "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
106 "key_magic2=3A+3C\0" \
107 "key_cmd2=echo *** Entering Update Mode ***;" \
108 "if fatload ide 0:3 10000 update.scr;" \
109 "then autoscr 10000;" \
110 "else echo *** UPDATE FAILED ***;" \
112 "key_magic3=3C+3F\0" \
113 "key_cmd3=echo *** Entering Test Mode ***;" \
114 "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
115 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
116 "ramargs=setenv bootargs root=/dev/ram rw\0" \
117 "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \
118 "addip=setenv bootargs $bootargs " \
119 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
121 "add_wdt=setenv bootargs $bootargs $wdt_args\0" \
122 "add_misc=setenv bootargs $bootargs runmode\0" \
123 "flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \
124 "bootm $kernel_addr\0" \
125 "flash_self=run ramargs addip add_wdt addfb add_misc;" \
126 "bootm $kernel_addr $ramdisk_addr\0" \
127 "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \
128 "run nfsargs addip add_wdt addfb;bootm\0" \
129 "rootpath=/opt/eldk/ppc_8xx\0" \
130 "load=tftp 100000 /tftpboot/u-boot.bin\0" \
131 "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
132 "wdt_args=wdt_8xx=off\0" \
135 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
136 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
138 #define CONFIG_WATCHDOG 1 /* watchdog enabled */
139 #define CFG_WATCHDOG_FREQ (CFG_HZ / 20)
141 #undef CONFIG_STATUS_LED /* Status LED disabled */
143 /* enable I2C and select the hardware/software driver */
144 #undef CONFIG_HARD_I2C /* I2C with hardware support */
145 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
147 #define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
148 #define CFG_I2C_SLAVE 0xFE
150 #ifdef CONFIG_SOFT_I2C
152 * Software (bit-bang) I2C driver configuration
154 #define PB_SCL 0x00000020 /* PB 26 */
155 #define PB_SDA 0x00000010 /* PB 27 */
157 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
158 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
159 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
160 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
161 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
162 else immr->im_cpm.cp_pbdat &= ~PB_SDA
163 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
164 else immr->im_cpm.cp_pbdat &= ~PB_SCL
165 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
166 #endif /* CONFIG_SOFT_I2C */
169 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
172 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
174 #define CFG_CMD_POST_DIAG 0
177 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
188 #define CONFIG_MAC_PARTITION
189 #define CONFIG_DOS_PARTITION
191 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
193 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
194 #include <cmd_confdefs.h>
196 /*----------------------------------------------------------------------*/
199 * Miscellaneous configurable options
201 #define CFG_LONGHELP /* undef to save memory */
202 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
204 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
205 #ifdef CFG_HUSH_PARSER
206 #define CFG_PROMPT_HUSH_PS2 "> "
209 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
210 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
212 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
214 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
215 #define CFG_MAXARGS 16 /* max number of command args */
216 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
218 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
219 #define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
221 #define CFG_LOAD_ADDR 0x00100000 /* default load address */
223 #define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
225 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
228 * When the watchdog is enabled, output must be fast enough in Linux.
230 #ifdef CONFIG_WATCHDOG
231 #define CFG_BAUDRATE_TABLE { 38400, 57600, 115200 }
233 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
236 /*----------------------------------------------------------------------*/
237 #define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */
238 #undef CONFIG_MODEM_SUPPORT_DEBUG
240 #define CONFIG_MODEM_KEY_MAGIC "3C+3D" /* press F3 + F4 keys to enable modem */
241 #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
243 #define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
244 #define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
245 #define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
247 /*----------------------------------------------------------------------*/
250 * Low Level Configuration Settings
251 * (address mappings, register initial values, etc.)
252 * You should know what you are doing if you make changes here.
254 /*-----------------------------------------------------------------------
255 * Internal Memory Mapped Register
257 #define CFG_IMMR 0xFFF00000
259 /*-----------------------------------------------------------------------
260 * Definitions for initial stack pointer and data area (in DPRAM)
262 #define CFG_INIT_RAM_ADDR CFG_IMMR
263 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
264 #define CFG_GBL_DATA_SIZE 68 /* size in bytes reserved for initial data */
265 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
266 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
268 /*-----------------------------------------------------------------------
269 * Start addresses for the final memory configuration
270 * (Set up by the startup code)
271 * Please note that CFG_SDRAM_BASE _must_ start at 0
273 #define CFG_SDRAM_BASE 0x00000000
274 #define CFG_FLASH_BASE 0x40000000
275 #if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
276 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
278 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
280 #define CFG_MONITOR_BASE CFG_FLASH_BASE
281 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
284 * For booting Linux, the board info and command line data
285 * have to be in the first 8 MB of memory, since this is
286 * the maximum mapped by the Linux kernel during initialization.
288 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
289 /*-----------------------------------------------------------------------
292 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
293 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
295 #define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
296 #define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
297 #define CFG_FLASH_USE_BUFFER_WRITE
298 #define CFG_FLASH_BUFFER_WRITE_TOUT 2048 /* Timeout for Flash Buffer Write (in ms) */
300 We have two flash devices connected in parallel.
301 Each device incorporates a Write Buffer of 32 bytes.
303 #define CFG_FLASH_BUFFER_SIZE (2*32)
305 /* Put environment in flash which is much faster to boot than using the EEPROM */
306 #define CFG_ENV_IS_IN_FLASH 1
307 #define CFG_ENV_ADDR 0x40040000 /* Address of Environment Sector */
308 #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */
309 #define CFG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */
311 /*-----------------------------------------------------------------------
312 * I2C/EEPROM Configuration
315 #define CFG_I2C_AUDIO_ADDR 0x28 /* Audio volume control */
316 #define CFG_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */
317 #define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
318 #define CFG_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */
319 #define CFG_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */
320 #define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
321 #define CFG_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */
323 #undef CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */
325 #ifdef CONFIG_USE_FRAM /* use FRAM */
326 #define CFG_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */
327 #define CFG_I2C_EEPROM_ADDR_LEN 2
328 #else /* use EEPROM */
329 #define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
330 #define CFG_I2C_EEPROM_ADDR_LEN 1
331 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
332 #endif /* CONFIG_USE_FRAM */
333 #define CFG_EEPROM_PAGE_WRITE_BITS 4
335 /* List of I2C addresses to be verified by POST */
336 #ifdef CONFIG_USE_FRAM
337 #define I2C_ADDR_LIST { /* CFG_I2C_AUDIO_ADDR, */ \
338 CFG_I2C_SYSMON_ADDR, \
340 CFG_I2C_POWER_A_ADDR, \
341 CFG_I2C_POWER_B_ADDR, \
342 CFG_I2C_KEYBD_ADDR, \
343 CFG_I2C_PICIO_ADDR, \
344 CFG_I2C_EEPROM_ADDR, \
346 #else /* Use EEPROM - which show up on 8 consequtive addresses */
347 #define I2C_ADDR_LIST { /* CFG_I2C_AUDIO_ADDR, */ \
348 CFG_I2C_SYSMON_ADDR, \
350 CFG_I2C_POWER_A_ADDR, \
351 CFG_I2C_POWER_B_ADDR, \
352 CFG_I2C_KEYBD_ADDR, \
353 CFG_I2C_PICIO_ADDR, \
354 CFG_I2C_EEPROM_ADDR+0, \
355 CFG_I2C_EEPROM_ADDR+1, \
356 CFG_I2C_EEPROM_ADDR+2, \
357 CFG_I2C_EEPROM_ADDR+3, \
358 CFG_I2C_EEPROM_ADDR+4, \
359 CFG_I2C_EEPROM_ADDR+5, \
360 CFG_I2C_EEPROM_ADDR+6, \
361 CFG_I2C_EEPROM_ADDR+7, \
363 #endif /* CONFIG_USE_FRAM */
365 /*-----------------------------------------------------------------------
366 * Cache Configuration
368 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
369 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
370 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
373 /*-----------------------------------------------------------------------
374 * SYPCR - System Protection Control 11-9
375 * SYPCR can only be written once after reset!
376 *-----------------------------------------------------------------------
377 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
379 #if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */
380 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
381 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
383 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
386 /*-----------------------------------------------------------------------
387 * SIUMCR - SIU Module Configuration 11-6
388 *-----------------------------------------------------------------------
389 * PCMCIA config., multi-function pin tri-state
391 /* EARB, DBGC and DBPC are initialised by the HCW */
393 #define CFG_SIUMCR (SIUMCR_GB5E)
394 /*#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
396 /*-----------------------------------------------------------------------
397 * TBSCR - Time Base Status and Control 11-26
398 *-----------------------------------------------------------------------
399 * Clear Reference Interrupt Status, Timebase freezing enabled
401 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
403 /*-----------------------------------------------------------------------
404 * PISCR - Periodic Interrupt Status and Control 11-31
405 *-----------------------------------------------------------------------
406 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
408 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
410 /*-----------------------------------------------------------------------
411 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
412 *-----------------------------------------------------------------------
413 * Reset PLL lock status sticky bit, timer expired status bit and timer
414 * interrupt status bit, set PLL multiplication factor !
417 #define CFG_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */
419 ( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
420 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
421 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
422 PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
425 #define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*13200000)
427 /*-----------------------------------------------------------------------
428 * SCCR - System Clock and reset Control Register 15-27
429 *-----------------------------------------------------------------------
430 * Set clock output, timebase and RTC source and divider,
431 * power management and some other internal clocks
433 #define SCCR_MASK SCCR_EBDF11
435 #define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
436 SCCR_RTDIV | SCCR_RTSEL | \
437 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
438 SCCR_EBDF00 | SCCR_DFSYNC00 | \
439 SCCR_DFBRG00 | SCCR_DFNL000 | \
440 SCCR_DFNH000 | SCCR_DFLCD100 | \
443 /*-----------------------------------------------------------------------
444 * RTCSC - Real-Time Clock Status and Control Register 11-27
445 *-----------------------------------------------------------------------
447 /* 0x00C3 => 0x0003 */
448 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
451 /*-----------------------------------------------------------------------
452 * RCCR - RISC Controller Configuration Register 19-4
453 *-----------------------------------------------------------------------
455 #define CFG_RCCR 0x0000
457 /*-----------------------------------------------------------------------
458 * RMDS - RISC Microcode Development Support Control Register
459 *-----------------------------------------------------------------------
463 /*-----------------------------------------------------------------------
466 *-----------------------------------------------------------------------
468 #define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
470 /*-----------------------------------------------------------------------
472 *-----------------------------------------------------------------------
475 #define CFG_PCMCIA_MEM_ADDR (0x50000000)
476 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
477 #define CFG_PCMCIA_DMA_ADDR (0x54000000)
478 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
479 #define CFG_PCMCIA_ATTRB_ADDR (0x58000000)
480 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
481 #define CFG_PCMCIA_IO_ADDR (0x5C000000)
482 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
484 /*-----------------------------------------------------------------------
485 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
486 *-----------------------------------------------------------------------
489 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
491 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
492 #undef CONFIG_IDE_LED /* LED for ide not supported */
493 #undef CONFIG_IDE_RESET /* reset for ide not supported */
495 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
496 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
498 #define CFG_ATA_IDE0_OFFSET 0x0000
500 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
502 /* Offset for data I/O */
503 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
505 /* Offset for normal register accesses */
506 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
508 /* Offset for alternate registers */
509 #define CFG_ATA_ALT_OFFSET 0x0100
511 #define CONFIG_SUPPORT_VFAT /* enable VFAT support */
513 /*-----------------------------------------------------------------------
515 *-----------------------------------------------------------------------
521 * Init Memory Controller:
523 * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
526 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
527 #define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */
529 /* used to re-map FLASH:
530 * restrict access enough to keep SRAM working (if any)
531 * but not too much to meddle with FLASH accesses
533 #define CFG_REMAP_OR_AM 0xFF000000 /* OR addr mask */
534 #define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
536 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
537 #define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK)
539 #define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
541 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
543 /* 16 bit, bank valid */
544 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
546 #define CFG_OR1_REMAP CFG_OR0_REMAP
547 #define CFG_OR1_PRELIM CFG_OR0_PRELIM
548 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
553 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
555 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
556 #define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */
557 #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
559 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */
561 #define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
562 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
565 * BR5/OR5: Touch Panel
567 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
569 #define TOUCHPNL_BASE 0x20000000
570 #define TOUCHPNL_OR_AM 0xFFFF8000
571 #define TOUCHPNL_TIMING OR_SCY_0_CLK
573 #define CFG_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
575 #define CFG_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
577 #define CFG_MEMORY_75
582 * Memory Periodic Timer Prescaler
585 /* periodic timer for refresh */
586 #define CFG_MPTPR 0x200
589 * MAMR settings for SDRAM
592 #define CFG_MAMR_8COL 0x80802114
593 #define CFG_MAMR_9COL 0x80904114
596 * MAR setting for SDRAM
598 #define CFG_MAR 0x00000088
601 * Internal Definitions
605 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
606 #define BOOTFLAG_WARM 0x02 /* Software reboot */
608 #endif /* __CONFIG_H */