3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 /* External logbuffer support */
32 #define CONFIG_LOGBUFFER
35 * High Level Configuration Options
39 #define CONFIG_MPC823 1 /* This is a MPC823E CPU */
40 #define CONFIG_LWMON 1 /* ...on a LWMON board */
42 #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
44 #define CONFIG_LCD 1 /* use LCD controller ... */
45 #define CONFIG_HLD1045 1 /* ... with a HLD1045 display */
48 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
50 #define CONFIG_8xx_CONS_SCC2
53 #define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */
55 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
57 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
59 /* pre-boot commands */
60 #define CONFIG_PREBOOT "setenv bootdelay 15"
62 #undef CONFIG_BOOTARGS
65 #define CONFIG_POST (CFG_POST_CACHE | \
77 #define CONFIG_BOOTCOMMAND "run flash_self"
79 #define CONFIG_EXTRA_ENV_SETTINGS \
80 "kernel_addr=40080000\0" \
81 "ramdisk_addr=40280000\0" \
84 "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
85 "key_magic3=3C+3F\0" \
86 "key_cmd3=echo *** Entering Test Mode ***;" \
87 "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
88 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
89 "ramargs=setenv bootargs root=/dev/ram rw\0" \
90 "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \
91 "addip=setenv bootargs $bootargs " \
92 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
94 "add_wdt=setenv bootargs $bootargs $wdt_args\0" \
95 "add_misc=setenv bootargs $bootargs runmode\0" \
96 "flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \
97 "bootm $kernel_addr\0" \
98 "flash_self=run ramargs addip add_wdt addfb add_misc;" \
99 "bootm $kernel_addr $ramdisk_addr\0" \
100 "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \
101 "run nfsargs addip add_wdt addfb;bootm\0" \
102 "rootpath=/opt/eldk/ppc_8xx\0" \
103 "load=tftp 100000 /tftpboot/u-boot.bin\0" \
104 "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
105 "wdt_args=wdt_8xx=off\0" \
108 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
109 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
111 #define CONFIG_WATCHDOG 1 /* watchdog enabled */
113 #undef CONFIG_STATUS_LED /* Status LED disabled */
115 /* enable I2C and select the hardware/software driver */
116 #undef CONFIG_HARD_I2C /* I2C with hardware support */
117 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
119 #define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
120 #define CFG_I2C_SLAVE 0xFE
122 #ifdef CONFIG_SOFT_I2C
124 * Software (bit-bang) I2C driver configuration
126 #define PB_SCL 0x00000020 /* PB 26 */
127 #define PB_SDA 0x00000010 /* PB 27 */
129 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
130 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
131 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
132 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
133 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
134 else immr->im_cpm.cp_pbdat &= ~PB_SDA
135 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
136 else immr->im_cpm.cp_pbdat &= ~PB_SCL
137 #define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */
138 #endif /* CONFIG_SOFT_I2C */
141 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
144 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
146 #define CFG_CMD_POST_DIAG 0
149 #ifdef CONFIG_8xx_CONS_SCC2 /* Can't use ethernet, then */
150 #define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \
159 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
169 #define CONFIG_MAC_PARTITION
170 #define CONFIG_DOS_PARTITION
172 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
174 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
175 #include <cmd_confdefs.h>
177 /*----------------------------------------------------------------------*/
180 * Miscellaneous configurable options
182 #define CFG_LONGHELP /* undef to save memory */
183 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
185 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
187 #ifdef CFG_HUSH_PARSER
188 #define CFG_PROMPT_HUSH_PS2 "> "
190 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
191 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
193 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
195 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
196 #define CFG_MAXARGS 16 /* max number of command args */
197 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
199 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
200 #define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
202 #define CFG_LOAD_ADDR 0x00100000 /* default load address */
204 #define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
206 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
209 * When the watchdog is enabled, output must be fast enough in Linux.
211 #ifdef CONFIG_WATCHDOG
212 #define CFG_BAUDRATE_TABLE { 38400, 57600, 115200 }
214 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
218 * Low Level Configuration Settings
219 * (address mappings, register initial values, etc.)
220 * You should know what you are doing if you make changes here.
222 /*-----------------------------------------------------------------------
223 * Internal Memory Mapped Register
225 #define CFG_IMMR 0xFFF00000
227 /*-----------------------------------------------------------------------
228 * Definitions for initial stack pointer and data area (in DPRAM)
230 #define CFG_INIT_RAM_ADDR CFG_IMMR
231 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
232 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
233 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
234 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
236 /*-----------------------------------------------------------------------
237 * Start addresses for the final memory configuration
238 * (Set up by the startup code)
239 * Please note that CFG_SDRAM_BASE _must_ start at 0
241 #define CFG_SDRAM_BASE 0x00000000
242 #define CFG_FLASH_BASE 0x40000000
243 #if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
244 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
246 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
248 #define CFG_MONITOR_BASE CFG_FLASH_BASE
249 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
252 * For booting Linux, the board info and command line data
253 * have to be in the first 8 MB of memory, since this is
254 * the maximum mapped by the Linux kernel during initialization.
256 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
257 /*-----------------------------------------------------------------------
260 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
261 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
263 #define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
264 #define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
267 /* Put environment in flash which is much faster to boot */
268 #define CFG_ENV_IS_IN_FLASH 1
269 #define CFG_ENV_ADDR 0x40040000 /* Address of Environment Sector */
270 #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */
271 #define CFG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */
273 /* Environment in EEPROM */
274 #define CFG_ENV_IS_IN_EEPROM 1
275 #define CFG_ENV_OFFSET 0
276 #define CFG_ENV_SIZE 2048
278 /*-----------------------------------------------------------------------
279 * I2C/EEPROM Configuration
282 #define CFG_I2C_AUDIO_ADDR 0x28 /* Audio volume control */
283 #define CFG_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */
284 #define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
285 #define CFG_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */
286 #define CFG_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */
287 #define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
288 #define CFG_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */
290 #undef CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */
292 #ifdef CONFIG_USE_FRAM /* use FRAM */
293 #define CFG_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */
294 #define CFG_I2C_EEPROM_ADDR_LEN 2
295 #else /* use EEPROM */
296 #define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
297 #define CFG_I2C_EEPROM_ADDR_LEN 1
298 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
299 #endif /* CONFIG_USE_FRAM */
300 #define CFG_EEPROM_PAGE_WRITE_BITS 4
302 /* List of I2C addresses to be verified by POST */
303 #ifdef CONFIG_USE_FRAM
304 #define I2C_ADDR_LIST { /* CFG_I2C_AUDIO_ADDR, */ \
305 CFG_I2C_SYSMON_ADDR, \
307 CFG_I2C_POWER_A_ADDR, \
308 CFG_I2C_POWER_B_ADDR, \
309 CFG_I2C_KEYBD_ADDR, \
310 CFG_I2C_PICIO_ADDR, \
311 CFG_I2C_EEPROM_ADDR, \
313 #else /* Use EEPROM - which show up on 8 consequtive addresses */
314 #define I2C_ADDR_LIST { /* CFG_I2C_AUDIO_ADDR, */ \
315 CFG_I2C_SYSMON_ADDR, \
317 CFG_I2C_POWER_A_ADDR, \
318 CFG_I2C_POWER_B_ADDR, \
319 CFG_I2C_KEYBD_ADDR, \
320 CFG_I2C_PICIO_ADDR, \
321 CFG_I2C_EEPROM_ADDR+0, \
322 CFG_I2C_EEPROM_ADDR+1, \
323 CFG_I2C_EEPROM_ADDR+2, \
324 CFG_I2C_EEPROM_ADDR+3, \
325 CFG_I2C_EEPROM_ADDR+4, \
326 CFG_I2C_EEPROM_ADDR+5, \
327 CFG_I2C_EEPROM_ADDR+6, \
328 CFG_I2C_EEPROM_ADDR+7, \
330 #endif /* CONFIG_USE_FRAM */
332 /*-----------------------------------------------------------------------
333 * Cache Configuration
335 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
336 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
337 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
340 /*-----------------------------------------------------------------------
341 * SYPCR - System Protection Control 11-9
342 * SYPCR can only be written once after reset!
343 *-----------------------------------------------------------------------
344 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
346 #if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */
347 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
348 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
350 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
353 /*-----------------------------------------------------------------------
354 * SIUMCR - SIU Module Configuration 11-6
355 *-----------------------------------------------------------------------
356 * PCMCIA config., multi-function pin tri-state
358 /* EARB, DBGC and DBPC are initialised by the HCW */
360 #define CFG_SIUMCR (SIUMCR_GB5E)
361 /*#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
363 /*-----------------------------------------------------------------------
364 * TBSCR - Time Base Status and Control 11-26
365 *-----------------------------------------------------------------------
366 * Clear Reference Interrupt Status, Timebase freezing enabled
368 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
370 /*-----------------------------------------------------------------------
371 * PISCR - Periodic Interrupt Status and Control 11-31
372 *-----------------------------------------------------------------------
373 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
375 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
377 /*-----------------------------------------------------------------------
378 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
379 *-----------------------------------------------------------------------
380 * Reset PLL lock status sticky bit, timer expired status bit and timer
381 * interrupt status bit, set PLL multiplication factor !
384 #define CFG_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */
386 ( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
387 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
388 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
389 PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
392 #define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*13200000)
394 /*-----------------------------------------------------------------------
395 * SCCR - System Clock and reset Control Register 15-27
396 *-----------------------------------------------------------------------
397 * Set clock output, timebase and RTC source and divider,
398 * power management and some other internal clocks
400 #define SCCR_MASK SCCR_EBDF11
402 #define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
403 SCCR_RTDIV | SCCR_RTSEL | \
404 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
405 SCCR_EBDF00 | SCCR_DFSYNC00 | \
406 SCCR_DFBRG00 | SCCR_DFNL000 | \
407 SCCR_DFNH000 | SCCR_DFLCD100 | \
410 /*-----------------------------------------------------------------------
411 * RTCSC - Real-Time Clock Status and Control Register 11-27
412 *-----------------------------------------------------------------------
414 /* 0x00C3 => 0x0003 */
415 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
418 /*-----------------------------------------------------------------------
419 * RCCR - RISC Controller Configuration Register 19-4
420 *-----------------------------------------------------------------------
422 #define CFG_RCCR 0x0000
424 /*-----------------------------------------------------------------------
425 * RMDS - RISC Microcode Development Support Control Register
426 *-----------------------------------------------------------------------
430 /*-----------------------------------------------------------------------
433 *-----------------------------------------------------------------------
435 #define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
437 /*-----------------------------------------------------------------------
439 *-----------------------------------------------------------------------
442 #define CFG_PCMCIA_MEM_ADDR (0x50000000)
443 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
444 #define CFG_PCMCIA_DMA_ADDR (0x54000000)
445 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
446 #define CFG_PCMCIA_ATTRB_ADDR (0x58000000)
447 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
448 #define CFG_PCMCIA_IO_ADDR (0x5C000000)
449 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
451 /*-----------------------------------------------------------------------
452 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
453 *-----------------------------------------------------------------------
456 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
458 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
459 #undef CONFIG_IDE_LED /* LED for ide not supported */
460 #undef CONFIG_IDE_RESET /* reset for ide not supported */
462 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
463 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
465 #define CFG_ATA_IDE0_OFFSET 0x0000
467 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
469 /* Offset for data I/O */
470 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
472 /* Offset for normal register accesses */
473 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
475 /* Offset for alternate registers */
476 #define CFG_ATA_ALT_OFFSET 0x0100
478 /*-----------------------------------------------------------------------
480 *-----------------------------------------------------------------------
483 /*#define CFG_DER 0x2002000F*/
487 * Init Memory Controller:
489 * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
492 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
493 #define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */
495 /* used to re-map FLASH:
496 * restrict access enough to keep SRAM working (if any)
497 * but not too much to meddle with FLASH accesses
499 #define CFG_REMAP_OR_AM 0xFF000000 /* OR addr mask */
500 #define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
502 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
503 #define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK)
505 #define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
507 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
509 /* 16 bit, bank valid */
510 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
512 #define CFG_OR1_REMAP CFG_OR0_REMAP
513 #define CFG_OR1_PRELIM CFG_OR0_PRELIM
514 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
519 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
521 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
522 #define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */
523 #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
525 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */
527 #define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
528 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
531 * BR5/OR5: Touch Panel
533 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
535 #define TOUCHPNL_BASE 0x20000000
536 #define TOUCHPNL_OR_AM 0xFFFF8000
537 #define TOUCHPNL_TIMING OR_SCY_0_CLK
539 #define CFG_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
541 #define CFG_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
543 #define CFG_MEMORY_75
548 * Memory Periodic Timer Prescaler
551 /* periodic timer for refresh */
552 #define CFG_MPTPR 0x200
555 * MAMR settings for SDRAM
558 #define CFG_MAMR_8COL 0x80802114
559 #define CFG_MAMR_9COL 0x80904114
562 * MAR setting for SDRAM
564 #define CFG_MAR 0x00000088
567 * Internal Definitions
571 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
572 #define BOOTFLAG_WARM 0x02 /* Software reboot */
574 #endif /* __CONFIG_H */