2 * Aries M53 configuration
3 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __M53EVK_CONFIG_H__
9 #define __M53EVK_CONFIG_H__
11 #define CONFIG_MXC_GPIO
13 #include <asm/arch/imx-regs.h>
15 #define CONFIG_REVISION_TAG
16 #define CONFIG_SYS_FSL_CLK
18 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
23 #define CONFIG_CMD_NAND
24 #define CONFIG_CMD_NAND_TRIMFFS
27 * Memory configurations
29 #define CONFIG_NR_DRAM_BANKS 2
30 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
31 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
32 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
33 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
34 #define PHYS_SDRAM_SIZE (gd->ram_size)
35 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
36 #define CONFIG_SYS_MEMTEST_START 0x70000000
37 #define CONFIG_SYS_MEMTEST_END 0x8ff00000
39 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
40 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
41 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
43 #define CONFIG_SYS_INIT_SP_OFFSET \
44 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
45 #define CONFIG_SYS_INIT_SP_ADDR \
46 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
48 #define CONFIG_SYS_TEXT_BASE 0x71000000
51 * U-Boot general configurations
53 #define CONFIG_SYS_LONGHELP
54 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
55 #define CONFIG_SYS_PBSIZE \
56 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
57 /* Print buffer size */
58 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
59 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
60 /* Boot argument buffer size */
61 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
62 #define CONFIG_CMDLINE_EDITING /* Command history etc */
67 #define CONFIG_MXC_UART
68 #define CONFIG_MXC_UART_BASE UART2_BASE
69 #define CONFIG_CONS_INDEX 1
75 #define CONFIG_FSL_ESDHC
76 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
77 #define CONFIG_SYS_FSL_ESDHC_NUM 1
83 #define CONFIG_ENV_SIZE (16 * 1024)
84 #ifdef CONFIG_CMD_NAND
85 #define CONFIG_SYS_MAX_NAND_DEVICE 1
86 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
87 #define CONFIG_NAND_MXC
88 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
89 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
90 #define CONFIG_SYS_NAND_LARGEPAGE
91 #define CONFIG_MXC_NAND_HWECC
92 #define CONFIG_SYS_NAND_USE_FLASH_BBT
94 /* Environment is in NAND */
95 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
96 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
97 #define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE)
98 #define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */
99 #define CONFIG_ENV_OFFSET_REDUND \
100 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
102 #define CONFIG_MTD_DEVICE
103 #define CONFIG_MTD_PARTITIONS
104 #define MTDIDS_DEFAULT "nand0=mxc_nand"
105 #define MTDPARTS_DEFAULT \
106 "mtdparts=mxc_nand:" \
116 * Ethernet on SOC (FEC)
118 #ifdef CONFIG_CMD_NET
119 #define CONFIG_FEC_MXC
120 #define IMX_FEC_BASE FEC_BASE_ADDR
121 #define CONFIG_FEC_MXC_PHYADDR 0x0
123 #define CONFIG_DISCOVER_PHY
124 #define CONFIG_FEC_XCV_TYPE RMII
125 #define CONFIG_PHYLIB
126 #define CONFIG_PHY_MICREL
127 #define CONFIG_ETHPRIME "FEC0"
133 #ifdef CONFIG_CMD_I2C
134 #define CONFIG_SYS_I2C
135 #define CONFIG_SYS_I2C_MXC
136 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
137 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
138 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
139 #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
145 #ifdef CONFIG_CMD_DATE
146 #define CONFIG_RTC_M41T62
147 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
148 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
154 #ifdef CONFIG_CMD_USB
155 #define CONFIG_USB_EHCI_MX5
156 #define CONFIG_USB_HOST_ETHER
157 #define CONFIG_USB_ETHER_ASIX
158 #define CONFIG_USB_ETHER_MCS7830
159 #define CONFIG_USB_ETHER_SMSC95XX
160 #define CONFIG_MXC_USB_PORT 1
161 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
162 #define CONFIG_MXC_USB_FLAGS 0
168 #ifdef CONFIG_CMD_SATA
169 #define CONFIG_DWC_AHSATA
170 #define CONFIG_SYS_SATA_MAX_DEVICE 1
171 #define CONFIG_DWC_AHSATA_PORT_ID 0
172 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
174 #define CONFIG_LIBATA
181 #define CONFIG_VIDEO_IPUV3
182 #define CONFIG_VIDEO_BMP_RLE8
183 #define CONFIG_VIDEO_BMP_GZIP
184 #define CONFIG_SPLASH_SCREEN
185 #define CONFIG_SPLASHIMAGE_GUARD
186 #define CONFIG_SPLASH_SCREEN_ALIGN
187 #define CONFIG_BMP_16BPP
188 #define CONFIG_VIDEO_LOGO
189 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
190 #define CONFIG_IPUV3_CLK 200000000
196 #define CONFIG_CMDLINE_TAG
197 #define CONFIG_INITRD_TAG
198 #define CONFIG_REVISION_TAG
199 #define CONFIG_SETUP_MEMORY_TAGS
200 #define CONFIG_BOOTFILE "fitImage"
201 #define CONFIG_BOOTARGS "console=ttymxc1,115200"
202 #define CONFIG_LOADADDR 0x70800000
203 #define CONFIG_BOOTCOMMAND "run mmc_mmc"
204 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
209 #define CONFIG_SPL_FRAMEWORK
210 #define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
211 #define CONFIG_SPL_TEXT_BASE 0x70008000
212 #define CONFIG_SPL_PAD_TO 0x8000
213 #define CONFIG_SPL_STACK 0x70004000
215 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
216 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
217 #define CONFIG_SYS_NAND_OOBSIZE 64
218 #define CONFIG_SYS_NAND_PAGE_COUNT 64
219 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
220 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
225 #define CONFIG_PREBOOT "run try_bootscript"
226 #define CONFIG_HOSTNAME m53evk
228 #define CONFIG_EXTRA_ENV_SETTINGS \
229 "consdev=ttymxc1\0" \
230 "baudrate=115200\0" \
231 "bootscript=boot.scr\0" \
232 "bootdev=/dev/mmcblk0p1\0" \
233 "rootdev=/dev/mmcblk0p2\0" \
235 "rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-qte-sdk\0" \
236 "kernel_addr_r=0x72000000\0" \
238 "setenv bootargs ${bootargs} " \
239 "console=${consdev},${baudrate}\0" \
241 "setenv bootargs ${bootargs} " \
242 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
243 "${netmask}:${hostname}:${netdev}:off\0" \
245 "setenv bootargs ${bootargs} ${miscargs}\0" \
247 "if test \"x${mtdparts}\" == \"x\" ; then " \
248 "mtdparts default ; " \
251 "run adddfltmtd ; " \
252 "setenv bootargs ${bootargs} ${mtdparts}\0" \
253 "addargs=run addcons addmtd addmisc\0" \
256 "load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \
258 "ubi part UBI ; ubifsmount ubi0:rootfs ; " \
259 "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
261 "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
262 "miscargs=nohlt panic=1\0" \
263 "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
265 "setenv bootargs ubi.mtd=5 " \
266 "root=ubi0:rootfs rootfstype=ubifs\0" \
268 "setenv bootargs root=/dev/nfs rw " \
269 "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
271 "run mmcload mmcargs addargs ; " \
272 "bootm ${kernel_addr_r}\0" \
274 "run mmcload ubiargs addargs ; " \
275 "bootm ${kernel_addr_r}\0" \
277 "run mmcload nfsargs addip addargs ; " \
278 "bootm ${kernel_addr_r}\0" \
280 "run ubiload mmcargs addargs ; " \
281 "bootm ${kernel_addr_r}\0" \
283 "run ubiload ubiargs addargs ; " \
284 "bootm ${kernel_addr_r}\0" \
286 "run ubiload nfsargs addip addargs ; " \
287 "bootm ${kernel_addr_r}\0" \
289 "run netload mmcargs addargs ; " \
290 "bootm ${kernel_addr_r}\0" \
292 "run netload ubiargs addargs ; " \
293 "bootm ${kernel_addr_r}\0" \
295 "run netload nfsargs addip addargs ; " \
296 "bootm ${kernel_addr_r}\0" \
299 "if test -e mmc 0:1 ${bootscript} ; then " \
300 "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
302 "echo Running bootscript... ; " \
303 "source ${kernel_addr_r} ; " \
307 #endif /* __M53EVK_CONFIG_H__ */