git.sur5r.net Git - u-boot/blob - include/configs/mgcoge.h

   1 /*
   2  * (C) Copyright 2007-2011
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC8247
  33 #define CONFIG_MGCOGE
  34 #define CONFIG_HOSTNAME         mgcoge
  35
  36 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  37
  38 /* include common defines/options for all Keymile boards */
  39 #include "keymile-common.h"
  40
  41 /*
  42  * Select serial console configuration
  43  *
  44  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  45  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  46  * for SCC).
  47  */
  48 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  49 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  50 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  51 #define CONFIG_CONS_INDEX       2       /* SMC2 is used for console  */
  52 #define CONFIG_SYS_SMC_RXBUFLEN 128
  53 #define CONFIG_SYS_MAXIDLE      10
  54
  55 /*
  56  * Select ethernet configuration
  57  *
  58  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  59  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  60  * SCC, 1-3 for FCC)
  61  *
  62  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  63  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  64  * must be unset.
  65  */
  66 #define CONFIG_ETHER_ON_SCC             /* Ethernet is on SCC */
  67 #undef  CONFIG_ETHER_ON_FCC             /* Ethernet is not on FCC     */
  68 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  69 #define CONFIG_NET_MULTI
  70
  71 #define CONFIG_ETHER_INDEX      4
  72 #define CONFIG_HAS_ETH0
  73 #define CONFIG_SYS_SCC_TOUT_LOOP        10000000
  74
  75 # define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
  76
  77 #ifndef CONFIG_8260_CLKIN
  78 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
  79 #endif
  80
  81 #define BOOTFLASH_START         0xFE000000
  82
  83 #define MTDIDS_DEFAULT          "nor0=boot,nor1=app"
  84 #define MTDPARTS_DEFAULT        \
  85         "mtdparts=boot:384k(u-boot),128k(env),128k(envred),3456k(free);" \
  86         "app:3m(esw0),10m(rootfs0),3m(esw1),10m(rootfs1),1m(var),5m(cfg)"
  87
  88 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
  89 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
  90 #endif
  91 /*
  92  * Default environment settings
  93  */
  94 #define CONFIG_EXTRA_ENV_SETTINGS       \
  95         CONFIG_KM_DEF_ENV                                               \
  96         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  97         "addcon=setenv bootargs ${bootargs} "                           \
  98                 "console=ttyCPM0,${baudrate}\0"                         \
  99         "mtdids=nor0=boot,nor1=app \0"                                  \
 100         "partition=nor1,5 \0"                                           \
 101         "new_env=prot off FE060000 FE09FFFF; era FE060000 FE09FFFF \0"  \
 102         "EEprom_ivm=pca9544a:70:4 \0"                                   \
 103         "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"                       \
 104         "unlock=yes\0"                                                  \
 105         ""
 106
 107 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 108 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 109 #define CONFIG_SYS_FLASH_SIZE           32
 110 #define CONFIG_SYS_FLASH_CFI
 111 #define CONFIG_FLASH_CFI_DRIVER
 112 #define CONFIG_SYS_MAX_FLASH_BANKS      3
 113 /* max num of sects on one chip */
 114 #define CONFIG_SYS_MAX_FLASH_SECT       512
 115
 116 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
 117 #define CONFIG_SYS_FLASH_SIZE_1 32
 118 #define CONFIG_SYS_FLASH_BASE_2 0x52000000
 119 #define CONFIG_SYS_FLASH_SIZE_2 32
 120
 121 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
 122                                         CONFIG_SYS_FLASH_BASE_1, \
 123                                         CONFIG_SYS_FLASH_BASE_2 }
 124
 125 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 126 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 127 #define CONFIG_SYS_RAMBOOT
 128 #endif
 129
 130 #define CONFIG_SYS_MONITOR_LEN          (768 << 10)
 131
 132 #define CONFIG_ENV_IS_IN_FLASH
 133
 134 #ifdef CONFIG_ENV_IS_IN_FLASH
 135 #define CONFIG_ENV_SECT_SIZE    0x20000
 136 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 137                                 CONFIG_SYS_MONITOR_LEN)
 138 #define CONFIG_ENV_OFFSET       CONFIG_SYS_MONITOR_LEN
 139
 140 /* Address and size of Redundant Environment Sector     */
 141 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 142                                         CONFIG_ENV_SECT_SIZE)
 143 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 144 #endif /* CONFIG_ENV_IS_IN_FLASH */
 145 #define CONFIG_ENV_BUFFER_PRINT
 146
 147 /* enable I2C and select the hardware/software driver */
 148 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 149 #define CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 150 #define CONFIG_SYS_I2C_SPEED            50000   /* I2C speed and slave address  */
 151 #define CONFIG_SYS_I2C_SLAVE            0x7F
 152
 153 /*
 154  * Software (bit-bang) I2C driver configuration
 155  */
 156
 157 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 158 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 159 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 160 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 161 #define I2C_SDA(bit)    do { \
 162                                 if (bit) \
 163                                         iop->pdat |=  0x00010000; \
 164                                 else \
 165                                         iop->pdat &= ~0x00010000; \
 166                         } while (0)
 167 #define I2C_SCL(bit)    do { \
 168                                 if (bit) \
 169                                         iop->pdat |=  0x00020000; \
 170                                 else \
 171                                         iop->pdat &= ~0x00020000; \
 172                         } while (0)
 173 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 174
 175 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
 176 #define CONFIG_DTT_LM75         /* ON Semi's LM75 */
 177 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses */
 178 #define CONFIG_SYS_DTT_MAX_TEMP 70
 179 #define CONFIG_SYS_DTT_LOW_TEMP -30
 180 #define CONFIG_SYS_DTT_HYSTERESIS       3
 181 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 182
 183 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 184
 185 #define CONFIG_SYS_IMMR         0xF0000000
 186
 187 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 188 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000
 189 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 190                                         GENERATED_GBL_DATA_SIZE)
 191 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 192
 193 /* Hard reset configuration word */
 194 #define CONFIG_SYS_HRCW_MASTER          0x0604b211
 195
 196 /* No slaves */
 197 #define CONFIG_SYS_HRCW_SLAVE1          0
 198 #define CONFIG_SYS_HRCW_SLAVE2          0
 199 #define CONFIG_SYS_HRCW_SLAVE3          0
 200 #define CONFIG_SYS_HRCW_SLAVE4          0
 201 #define CONFIG_SYS_HRCW_SLAVE5          0
 202 #define CONFIG_SYS_HRCW_SLAVE6          0
 203 #define CONFIG_SYS_HRCW_SLAVE7          0
 204
 205 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 206
 207 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 208 #if defined(CONFIG_CMD_KGDB)
 209 #  define CONFIG_SYS_CACHELINE_SHIFT    5 /* log base 2 of the above value */
 210 #endif
 211
 212 #define CONFIG_SYS_HID0_INIT            0
 213 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 214
 215 #define CONFIG_SYS_HID2         0
 216
 217 #define CONFIG_SYS_SIUMCR               0x4020c200
 218 #define CONFIG_SYS_SYPCR                0xFFFFFFC3
 219 #define CONFIG_SYS_BCR                  0x10000000
 220 #define CONFIG_SYS_SCCR         (SCCR_PCI_MODE | SCCR_PCI_MODCK)
 221
 222 /*
 223  *-----------------------------------------------------------------------
 224  * RMR - Reset Mode Register                                     5-5
 225  *-----------------------------------------------------------------------
 226  * turn on Checkstop Reset Enable
 227  */
 228 #define CONFIG_SYS_RMR         0
 229
 230 /*
 231  *-----------------------------------------------------------------------
 232  * TMCNTSC - Time Counter Status and Control                     4-40
 233  *-----------------------------------------------------------------------
 234  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 235  * and enable Time Counter
 236  */
 237 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 238
 239 /*
 240  *-----------------------------------------------------------------------
 241  * PISCR - Periodic Interrupt Status and Control                 4-42
 242  *-----------------------------------------------------------------------
 243  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 244  * Periodic timer
 245  */
 246 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 247
 248 /*
 249  *-----------------------------------------------------------------------
 250  * RCCR - RISC Controller Configuration                         13-7
 251  *-----------------------------------------------------------------------
 252  */
 253 #define CONFIG_SYS_RCCR        0
 254
 255 /*
 256  * Init Memory Controller:
 257  *
 258  * Bank Bus     Machine PortSz  Device
 259  * ---- ---     ------- ------  ------
 260  *  0   60x     GPCM     8 bit  FLASH
 261  *  1   60x     SDRAM   32 bit  SDRAM
 262  *  3   60x     GPCM     8 bit  GPIO/PIGGY
 263  *  5   60x     GPCM    16 bit  CFG-Flash
 264  *
 265  */
 266 /* Bank 0 - FLASH
 267  */
 268 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)    |\
 269                          BRx_PS_8                       |\
 270                          BRx_MS_GPCM_P                  |\
 271                          BRx_V)
 272
 273 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)        |\
 274                          ORxG_CSNT                      |\
 275                          ORxG_ACS_DIV2                  |\
 276                          ORxG_SCY_5_CLK                 |\
 277                          ORxG_TRLX )
 278
 279
 280 /*
 281  * Bank 1 - 60x bus SDRAM
 282  */
 283 #define SDRAM_MAX_SIZE  0x08000000      /* max. 128 MB          */
 284 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (256 << 20)
 285
 286 #define CONFIG_SYS_MPTPR       0x1800
 287
 288 /*
 289  *-----------------------------------------------------------------------------
 290  * Address for Mode Register Set (MRS) command
 291  *-----------------------------------------------------------------------------
 292  */
 293 #define CONFIG_SYS_MRS_OFFS     0x00000110
 294 #define CONFIG_SYS_PSRT        0x0e
 295
 296 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 297                          BRx_PS_64                      |\
 298                          BRx_MS_SDRAM_P                 |\
 299                          BRx_V)
 300
 301 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1
 302
 303 /*
 304  * SDRAM initialization values
 305  */
 306
 307 #define CONFIG_SYS_OR1    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 308                          ORxS_BPD_8                     |\
 309                          ORxS_ROWST_PBI0_A7             |\
 310                          ORxS_NUMR_13)
 311
 312 #define CONFIG_SYS_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
 313                          PSDMR_BSMA_A14_A16           |\
 314                          PSDMR_SDA10_PBI0_A9            |\
 315                          PSDMR_RFRC_5_CLK               |\
 316                          PSDMR_PRETOACT_2W              |\
 317                          PSDMR_ACTTORW_2W               |\
 318                          PSDMR_LDOTOPRE_1C              |\
 319                          PSDMR_WRC_1C                   |\
 320                          PSDMR_CL_2)
 321
 322 /*
 323  * GPIO/PIGGY on CS3 initialization values
 324  */
 325 #define CONFIG_SYS_PIGGY_BASE   0x30000000
 326 #define CONFIG_SYS_PIGGY_SIZE   128
 327
 328 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\
 329                          BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 330
 331 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\
 332                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 333                          ORxG_SCY_3_CLK | ORxG_TRLX )
 334
 335 /*
 336  * Board FPGA on CS4 initialization values
 337  */
 338 #define CONFIG_SYS_FPGA_BASE    0x40000000
 339 #define CONFIG_SYS_FPGA_SIZE    1 /*1KB*/
 340
 341 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
 342                         BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 343
 344 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
 345                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 346                          ORxG_SCY_3_CLK | ORxG_TRLX )
 347
 348 /*
 349  * CFG-Flash on CS5 initialization values
 350  */
 351 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
 352                          BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
 353
 354 #define CONFIG_SYS_OR5_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
 355                                  CONFIG_SYS_FLASH_SIZE_2) |\
 356                                  ORxG_CSNT | ORxG_ACS_DIV2 |\
 357                                  ORxG_SCY_5_CLK | ORxG_TRLX )
 358
 359 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address */
 360
 361 /* pass open firmware flat tree */
 362 #define CONFIG_FIT
 363 #define CONFIG_OF_LIBFDT
 364 #define CONFIG_OF_BOARD_SETUP
 365
 366 #define OF_TBCLK                (bd->bi_busfreq / 4)
 367 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a90"
 368
 369 /* enable last_stage_init */
 370 #define CONFIG_LAST_STAGE_INIT          1
 371 /* bfticu address */
 372 #define CONFIG_SYS_BFTICU_BASE          0x40000000
 373
 374 #endif /* __CONFIG_H */