2 * (C) Copyright 2007-2009 DENX Software Engineering
4 * SPDX-License-Identifier: GPL-2.0+
8 * MPC5121ADS board configuration file
14 #define CONFIG_MPC5121ADS 1
17 * Memory map for the MPC5121ADS board:
19 * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
20 * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
21 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
22 * 0x8200_0000 - 0x8200_001F CPLD (32 B)
23 * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
24 * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
25 * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
26 * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
30 * High Level Configuration Options
32 #define CONFIG_E300 1 /* E300 Family */
34 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
37 #ifdef CONFIG_FSL_DIU_FB
38 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100)
39 #define CONFIG_CMD_BMP
40 #define CONFIG_VIDEO_LOGO
41 #define CONFIG_VIDEO_BMP_LOGO
44 /* CONFIG_PCI is defined at config time */
46 #ifdef CONFIG_MPC5121ADS_REV2
47 #define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */
49 #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
52 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
53 #define CONFIG_MISC_INIT_R
55 #define CONFIG_SYS_IMMR 0x80000000
57 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
58 #define CONFIG_SYS_MEMTEST_END 0x00400000
61 * DDR Setup - manually set all parameters as there's no SPD etc.
63 #ifdef CONFIG_MPC5121ADS_REV2
64 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
66 #define CONFIG_SYS_DDR_SIZE 512 /* MB */
68 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
69 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
70 #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
72 #define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
74 /* DDR Controller Configuration
77 * [31:31] MDDRC Soft Reset: Diabled
78 * [30:30] DRAM CKE pin: Enabled
79 * [29:29] DRAM CLK: Enabled
80 * [28:28] Command Mode: Enabled (For initialization only)
81 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
82 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
83 * [20:19] Read Test: DON'T USE
84 * [18:18] Self Refresh: Enabled
85 * [17:17] 16bit Mode: Disabled
86 * [16:13] Ready Delay: 2
87 * [12:12] Half DQS Delay: Disabled
88 * [11:11] Quarter DQS Delay: Disabled
89 * [10:08] Write Delay: 2
90 * [07:07] Early ODT: Disabled
91 * [06:06] On DIE Termination: Disabled
92 * [05:05] FIFO Overflow Clear: DON'T USE here
93 * [04:04] FIFO Underflow Clear: DON'T USE here
94 * [03:03] FIFO Overflow Pending: DON'T USE here
95 * [02:02] FIFO Underlfow Pending: DON'T USE here
96 * [01:01] FIFO Overlfow Enabled: Enabled
97 * [00:00] FIFO Underflow Enabled: Enabled
99 * [31:16] DRAM Refresh Time: 0 CSB clocks
100 * [15:8] DRAM Command Time: 0 CSB clocks
101 * [07:00] DRAM Precharge Time: 0 CSB clocks
105 * [20:17] DRAM tWRT1:
112 * [22:19] DRAM tRTW1:
118 #ifdef CONFIG_MPC5121ADS_REV2
119 #define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00
120 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168
121 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864
123 #define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00
124 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
125 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
127 #define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E
129 #define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00
130 #define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189
131 #define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864
133 #define CONFIG_SYS_DDRCMD_NOP 0x01380000
134 #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
135 #define CONFIG_SYS_DDRCMD_EM2 0x01020000
136 #define CONFIG_SYS_DDRCMD_EM3 0x01030000
137 #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000
138 #define CONFIG_SYS_DDRCMD_RFSH 0x01080000
140 #define DDRCMD_EMR_OCD(pr, ohm) ( \
141 (1 << 24) | /* MDDRC Command Request */ \
142 (1 << 16) | /* MODE Reg BA[2:0] */ \
143 (0 << 12) | /* Outputs 0=Enabled */ \
144 (0 << 11) | /* RDQS */ \
145 (1 << 10) | /* DQS# */ \
146 (pr << 7) | /* OCD prog 7=deflt,0=exit */ \
147 /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
148 ((ohm & 0x2) << 5)| /* Rtt1 */ \
149 (0 << 3) | /* additive posted CAS# */ \
150 ((ohm & 0x1) << 2)| /* Rtt0 */ \
151 (0 << 0) | /* Output Drive Strength */ \
152 (0 << 0)) /* DLL Enable 0=Normal */
154 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0)
155 #define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0)
157 #define DDRCMD_MODE_REG(cas, wr) ( \
158 (1 << 24) | /* MDDRC Command Request */ \
159 (0 << 16) | /* MODE Reg BA[2:0] */ \
160 ((wr-1) << 9)| /* Write Recovery */ \
161 (cas << 4) | /* CAS */ \
162 (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \
163 (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */
165 #define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3)
166 #define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4)
167 #define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8))
169 /* DDR Priority Manager Configuration */
170 #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
171 #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
172 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
173 #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
174 #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
175 #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
176 #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
177 #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
178 #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
179 #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
180 #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
181 #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
182 #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
183 #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
184 #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
185 #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
186 #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
187 #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
188 #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
189 #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
190 #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
191 #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
192 #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
195 * NOR FLASH on the Local Bus
197 #undef CONFIG_BKUP_FLASH
198 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
199 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
200 #ifdef CONFIG_BKUP_FLASH
201 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
202 #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */
204 #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
205 #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */
207 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
208 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
209 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
210 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
212 #undef CONFIG_SYS_FLASH_CHECKSUM
216 * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
218 #define CONFIG_CMD_NAND /* enable NAND support */
219 #define CONFIG_JFFS2_NAND /* with JFFS2 on it */
220 #define CONFIG_NAND_MPC5121_NFC
221 #define CONFIG_SYS_NAND_BASE 0x40000000
223 #define CONFIG_SYS_MAX_NAND_DEVICE 2
224 #define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
227 * Configuration parameters for MPC5121 NAND driver
229 #define CONFIG_FSL_NFC_WIDTH 1
230 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
231 #define CONFIG_FSL_NFC_SPARE_SIZE 64
232 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
235 * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
238 #define CONFIG_SYS_CPLD_BASE 0x82000000
239 #define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */
240 #define CONFIG_SYS_CS2_START CONFIG_SYS_CPLD_BASE
241 #define CONFIG_SYS_CS2_SIZE CONFIG_SYS_CPLD_SIZE
243 #define CONFIG_SYS_SRAM_BASE 0x30000000
244 #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
246 #define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
247 #define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
248 #define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */
250 /* Use SRAM for initial stack */
251 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */
252 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of used area in RAM */
254 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
255 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
257 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */
258 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
259 #ifdef CONFIG_FSL_DIU_FB
260 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
262 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
268 #define CONFIG_CONS_INDEX 1
271 * Serial console configuration
273 #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
274 #define CONFIG_SYS_PSC3
275 #if CONFIG_PSC_CONSOLE != 3
276 #error CONFIG_PSC_CONSOLE must be 3
278 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
279 #define CONFIG_SYS_BAUDRATE_TABLE \
280 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
282 #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
283 #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
284 #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
285 #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
287 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
292 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
293 CLOCK_SCCR1_DDR_EN | \
294 CLOCK_SCCR1_FEC_EN | \
295 CLOCK_SCCR1_LPC_EN | \
296 CLOCK_SCCR1_NFC_EN | \
297 CLOCK_SCCR1_PATA_EN | \
298 CLOCK_SCCR1_PCI_EN | \
299 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
300 CLOCK_SCCR1_PSCFIFO_EN | \
303 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
304 CLOCK_SCCR2_I2C_EN | \
305 CLOCK_SCCR2_MEM_EN | \
306 CLOCK_SCCR2_SPDIF_EN | \
307 CLOCK_SCCR2_USB1_EN | \
314 #define CONFIG_PCI_INDIRECT_BRIDGE
319 #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
320 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
321 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
322 #define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
323 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
324 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
325 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
326 #define CONFIG_SYS_PCI_IO_PHYS 0x84000000
327 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
329 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
334 #define CONFIG_HARD_I2C /* I2C with hardware support */
335 #define CONFIG_I2C_MULTI_BUS
336 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
337 #define CONFIG_SYS_I2C_SLAVE 0x7F
339 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
343 * IIM - IC Identification Module
345 #undef CONFIG_FSL_IIM
348 * EEPROM configuration
350 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
351 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
352 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
353 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
356 * Ethernet configuration
358 #define CONFIG_MPC512x_FEC 1
359 #define CONFIG_PHY_ADDR 0x1
360 #define CONFIG_MII 1 /* MII PHY management */
361 #define CONFIG_FEC_AN_TIMEOUT 1
362 #define CONFIG_HAS_ETH0
365 * Configure on-board RTC
367 #define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */
368 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
374 #if defined(CONFIG_CMD_USB)
375 #define CONFIG_USB_EHCI /* Enable EHCI Support */
376 #define CONFIG_USB_EHCI_FSL /* On a FSL platform */
377 #define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */
378 #define CONFIG_EHCI_DESC_BIG_ENDIAN
379 #define CONFIG_EHCI_IS_TDI
385 #define CONFIG_ENV_IS_IN_FLASH 1
386 /* This has to be a multiple of the Flash sector size */
387 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
388 #define CONFIG_ENV_SIZE 0x2000
389 #ifdef CONFIG_BKUP_FLASH
390 #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */
392 #define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
395 /* Address and size of Redundant Environment Sector */
396 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
397 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
399 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
400 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
402 #define CONFIG_CMD_DATE
403 #define CONFIG_CMD_EEPROM
404 #define CONFIG_CMD_IDE
405 #define CONFIG_CMD_JFFS2
406 #define CONFIG_CMD_REGINFO
408 #undef CONFIG_CMD_FUSE
410 #if defined(CONFIG_PCI)
411 #define CONFIG_CMD_PCI
415 * Dynamic MTD partition support
417 #define CONFIG_CMD_MTDPARTS
418 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
419 #define CONFIG_FLASH_CFI_MTD
420 #define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand"
425 * FC000000 - FEABFFFF 42.75 MiB User Data
426 * FEAC0000 - FFABFFFF 16 MiB Root File System
427 * FFAC0000 - FFEBFFFF 4 MiB Linux Kernel
428 * FFEC0000 - FFEFFFFF 256 KiB Device Tree
429 * FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env
431 * NAND flash layout: one big partition
433 #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \
438 "mpc5121.nand:-(data)"
440 #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
442 #define CONFIG_DOS_PARTITION
443 #define CONFIG_MAC_PARTITION
444 #define CONFIG_ISO_PARTITION
446 #define CONFIG_SUPPORT_VFAT
448 #endif /* defined(CONFIG_CMD_IDE) */
451 * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
452 * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
453 * to 0xFFFF, watchdog timeouts after about 64s. For details refer
454 * to chapter 36 of the MPC5121e Reference Manual.
456 /* #define CONFIG_WATCHDOG */ /* enable watchdog */
457 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
460 * Miscellaneous configurable options
462 #define CONFIG_SYS_LONGHELP /* undef to save memory */
463 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
465 #ifdef CONFIG_CMD_KGDB
466 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
468 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
471 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
472 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
473 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
476 * For booting Linux, the board info and command line data
477 * have to be in the first 256 MB of memory, since this is
478 * the maximum mapped by the Linux kernel during initialization.
480 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
482 /* Cache Configuration */
483 #define CONFIG_SYS_DCACHE_SIZE 32768
484 #define CONFIG_SYS_CACHELINE_SIZE 32
485 #ifdef CONFIG_CMD_KGDB
486 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
489 #define CONFIG_SYS_HID0_INIT 0x000000000
490 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
491 #define CONFIG_SYS_HID2 HID2_HBE
493 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
495 #ifdef CONFIG_CMD_KGDB
496 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
500 * Environment Configuration
502 #define CONFIG_TIMESTAMP
504 #define CONFIG_HOSTNAME mpc5121ads
505 #define CONFIG_BOOTFILE "mpc5121ads/uImage"
506 #define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
508 #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
510 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
512 #define CONFIG_BAUDRATE 115200
514 #define CONFIG_PREBOOT "echo;" \
515 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
518 #define CONFIG_EXTRA_ENV_SETTINGS \
519 "u-boot_addr_r=200000\0" \
520 "kernel_addr_r=600000\0" \
521 "fdt_addr_r=880000\0" \
522 "ramdisk_addr_r=900000\0" \
523 "u-boot_addr=FFF00000\0" \
524 "kernel_addr=FFAC0000\0" \
525 "fdt_addr=FFEC0000\0" \
526 "ramdisk_addr=FEAC0000\0" \
527 "ramdiskfile=mpc5121ads/uRamdisk\0" \
528 "u-boot=mpc5121ads/u-boot.bin\0" \
529 "bootfile=mpc5121ads/uImage\0" \
530 "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \
531 "rootpath=/opt/eldk/ppc_6xx\n" \
533 "consdev=ttyPSC0\0" \
534 "nfsargs=setenv bootargs root=/dev/nfs rw " \
535 "nfsroot=${serverip}:${rootpath}\0" \
536 "ramargs=setenv bootargs root=/dev/ram rw\0" \
537 "addip=setenv bootargs ${bootargs} " \
538 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
539 ":${hostname}:${netdev}:off panic=1\0" \
540 "addtty=setenv bootargs ${bootargs} " \
541 "console=${consdev},${baudrate}\0" \
542 "flash_nfs=run nfsargs addip addtty;" \
543 "bootm ${kernel_addr} - ${fdt_addr}\0" \
544 "flash_self=run ramargs addip addtty;" \
545 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
546 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
547 "tftp ${fdt_addr_r} ${fdtfile};" \
548 "run nfsargs addip addtty;" \
549 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
550 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
551 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
552 "tftp ${fdt_addr_r} ${fdtfile};" \
553 "run ramargs addip addtty;" \
554 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
555 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
556 "update=protect off ${u-boot_addr} +${filesize};" \
557 "era ${u-boot_addr} +${filesize};" \
558 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
559 "upd=run load update\0" \
562 #define CONFIG_BOOTCOMMAND "run flash_self"
564 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
566 #define OF_CPU "PowerPC,5121@0"
567 #define OF_SOC_COMPAT "fsl,mpc5121-immr"
568 #define OF_TBCLK (bd->bi_busfreq / 4)
569 #define OF_STDOUT_PATH "/soc@80000000/serial@11300"
571 /*-----------------------------------------------------------------------
573 *-----------------------------------------------------------------------
576 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
577 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
578 #undef CONFIG_IDE_LED /* LED for IDE not supported */
580 #define CONFIG_IDE_RESET /* reset for IDE supported */
581 #define CONFIG_IDE_PREINIT
583 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
584 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
586 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
587 #define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
589 /* Offset for data I/O RefMan MPC5121EE Table 28-10 */
590 #define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
592 /* Offset for normal register accesses */
593 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
595 /* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
596 #define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
598 /* Interval between registers */
599 #define CONFIG_SYS_ATA_STRIDE 4
601 #define ATA_BASE_ADDR get_pata_base()
604 * Control register bit definitions
606 #define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
607 #define FSL_ATA_CTRL_ATA_RST_B 0x40000000
608 #define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
609 #define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
610 #define FSL_ATA_CTRL_DMA_PENDING 0x08000000
611 #define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
612 #define FSL_ATA_CTRL_DMA_WRITE 0x02000000
613 #define FSL_ATA_CTRL_IORDY_EN 0x01000000
615 #endif /* __CONFIG_H */