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[u-boot] / include / configs / mpc8308_p1m.h
1 /*
2  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
3  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
4  *
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 /*
13  * High Level Configuration Options
14  */
15 #define CONFIG_E300             1 /* E300 family */
16 #define CONFIG_MPC830x          1 /* MPC830x family */
17 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
18 #define CONFIG_MPC8308_P1M      1 /* mpc8308_p1m board specific */
19
20 #ifndef CONFIG_SYS_TEXT_BASE
21 #define CONFIG_SYS_TEXT_BASE    0xFC000000
22 #endif
23
24 /*
25  * On-board devices
26  *
27  * TSECs
28  */
29 #define CONFIG_TSEC1
30 #define CONFIG_TSEC2
31
32 /*
33  * System Clock Setup
34  */
35 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
36 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
37
38 /*
39  * Hardware Reset Configuration Word
40  * if CLKIN is 66.66MHz, then
41  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
42  * We choose the A type silicon as default, so the core is 400Mhz.
43  */
44 #define CONFIG_SYS_HRCW_LOW (\
45         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
46         HRCWL_DDR_TO_SCB_CLK_2X1 |\
47         HRCWL_SVCOD_DIV_2 |\
48         HRCWL_CSB_TO_CLKIN_4X1 |\
49         HRCWL_CORE_TO_CSB_3X1)
50 /*
51  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
52  * in 8308's HRCWH according to the manual, but original Freescale's
53  * code has them and I've expirienced some problems using the board
54  * with BDI3000 attached when I've tried to set these bits to zero
55  * (UART doesn't work after the 'reset run' command).
56  */
57 #define CONFIG_SYS_HRCW_HIGH (\
58         HRCWH_PCI_HOST |\
59         HRCWH_PCI1_ARBITER_ENABLE |\
60         HRCWH_CORE_ENABLE |\
61         HRCWH_FROM_0X00000100 |\
62         HRCWH_BOOTSEQ_DISABLE |\
63         HRCWH_SW_WATCHDOG_DISABLE |\
64         HRCWH_ROM_LOC_LOCAL_16BIT |\
65         HRCWH_RL_EXT_LEGACY |\
66         HRCWH_TSEC1M_IN_MII |\
67         HRCWH_TSEC2M_IN_MII |\
68         HRCWH_BIG_ENDIAN)
69
70 /*
71  * System IO Config
72  */
73 #define CONFIG_SYS_SICRH (\
74         SICRH_ESDHC_A_GPIO |\
75         SICRH_ESDHC_B_GPIO |\
76         SICRH_ESDHC_C_GTM |\
77         SICRH_GPIO_A_TSEC2 |\
78         SICRH_GPIO_B_TSEC2_TX_CLK |\
79         SICRH_IEEE1588_A_GPIO |\
80         SICRH_USB |\
81         SICRH_GTM_GPIO |\
82         SICRH_IEEE1588_B_GPIO |\
83         SICRH_ETSEC2_CRS |\
84         SICRH_GPIOSEL_1 |\
85         SICRH_TMROBI_V3P3 |\
86         SICRH_TSOBI1_V3P3 |\
87         SICRH_TSOBI2_V3P3)      /* 0xf577d100 */
88 #define CONFIG_SYS_SICRL (\
89         SICRL_SPI_PF0 |\
90         SICRL_UART_PF0 |\
91         SICRL_IRQ_PF0 |\
92         SICRL_I2C2_PF0 |\
93         SICRL_ETSEC1_TX_CLK)    /* 0x00000000 */
94
95 #define CONFIG_SYS_GPIO1_PRELIM
96 /* GPIO Default input/output settings */
97 #define CONFIG_SYS_GPIO1_DIR        0x7AAF8C00
98 /*
99  * Default GPIO values:
100  * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
101  */
102 #define CONFIG_SYS_GPIO1_DAT        0x08008C00
103
104 /*
105  * IMMR new address
106  */
107 #define CONFIG_SYS_IMMR         0xE0000000
108
109 /*
110  * SERDES
111  */
112 #define CONFIG_FSL_SERDES
113 #define CONFIG_FSL_SERDES1      0xe3000
114
115 /*
116  * Arbiter Setup
117  */
118 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
119 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
120 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
121
122 /*
123  * DDR Setup
124  */
125 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
126 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
127 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
128 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
129 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
130                                 | DDRCDR_PZ_LOZ \
131                                 | DDRCDR_NZ_LOZ \
132                                 | DDRCDR_ODT \
133                                 | DDRCDR_Q_DRN)
134                                 /* 0x7b880001 */
135 /*
136  * Manually set up DDR parameters
137  * consist of two chips HY5PS12621BFP-C4 from HYNIX
138  */
139
140 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
141
142 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
143 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
144                                         | CSCONFIG_ODT_RD_NEVER \
145                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
146                                         | CSCONFIG_ROW_BIT_13 \
147                                         | CSCONFIG_COL_BIT_10)
148                                         /* 0x80010102 */
149 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
150 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
151                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
152                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
153                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
154                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
155                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
156                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
157                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
158                                 /* 0x00220802 */
159 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
160                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
161                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
162                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
163                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
164                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
165                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
166                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
167                                 /* 0x27256222 */
168 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
169                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
170                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
171                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
172                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
173                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
174                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
175                                 /* 0x121048c5 */
176 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
177                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
178                                 /* 0x03600100 */
179 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
180                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
181                                 | SDRAM_CFG_DBW_32)
182                                 /* 0x43080000 */
183
184 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
185 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
186                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
187                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
188 #define CONFIG_SYS_DDR_MODE2            0x00000000
189
190 /*
191  * Memory test
192  */
193 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
194 #define CONFIG_SYS_MEMTEST_END          0x07f00000
195
196 /*
197  * The reserved memory
198  */
199 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
200
201 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
202 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
203
204 /*
205  * Initial RAM Base Address Setup
206  */
207 #define CONFIG_SYS_INIT_RAM_LOCK        1
208 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
209 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
210 #define CONFIG_SYS_GBL_DATA_OFFSET      \
211         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
212
213 /*
214  * Local Bus Configuration & Clock Setup
215  */
216 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
217 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
218 #define CONFIG_SYS_LBC_LBCR             0x00040000
219
220 /*
221  * FLASH on the Local Bus
222  */
223 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
224 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
225 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
226
227 #define CONFIG_SYS_FLASH_BASE           0xFC000000 /* FLASH base address */
228 #define CONFIG_SYS_FLASH_SIZE           64 /* FLASH size is 64M */
229 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
230
231 /* Window base at flash base */
232 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
233 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
234
235 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
236                                 | BR_PS_16      /* 16 bit port */ \
237                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
238                                 | BR_V)         /* valid */
239 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
240                                 | OR_UPM_XAM \
241                                 | OR_GPCM_CSNT \
242                                 | OR_GPCM_ACS_DIV2 \
243                                 | OR_GPCM_XACS \
244                                 | OR_GPCM_SCY_4 \
245                                 | OR_GPCM_TRLX_SET \
246                                 | OR_GPCM_EHTR_SET)
247
248 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
249 #define CONFIG_SYS_MAX_FLASH_SECT       512
250
251 /* Flash Erase Timeout (ms) */
252 #define CONFIG_SYS_FLASH_ERASE_TOUT     (1000 * 1024)
253 /* Flash Write Timeout (ms) */
254 #define CONFIG_SYS_FLASH_WRITE_TOUT     (500 * 1024)
255
256 /*
257  * SJA1000 CAN controller on Local Bus
258  */
259 #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
260 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_SJA1000_BASE \
261                                 | BR_PS_8       /* 8 bit port size */ \
262                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
263                                 | BR_V)         /* valid */
264 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
265                                 | OR_GPCM_SCY_5 \
266                                 | OR_GPCM_EHTR_SET)
267                                 /* 0xFFFF8052 */
268
269 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_SJA1000_BASE
270 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
271
272 /*
273  * CPLD on Local Bus
274  */
275 #define CONFIG_SYS_CPLD_BASE    0xFBFF8000
276 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_CPLD_BASE \
277                                 | BR_PS_8       /* 8 bit port */ \
278                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
279                                 | BR_V)         /* valid */
280 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB \
281                                 | OR_GPCM_SCY_4 \
282                                 | OR_GPCM_EHTR_SET)
283                                 /* 0xFFFF8042 */
284
285 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_CPLD_BASE
286 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
287
288 /*
289  * Serial Port
290  */
291 #define CONFIG_CONS_INDEX       1
292 #undef CONFIG_SERIAL_SOFTWARE_FIFO
293 #define CONFIG_SYS_NS16550_SERIAL
294 #define CONFIG_SYS_NS16550_REG_SIZE     1
295 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
296
297 #define CONFIG_SYS_BAUDRATE_TABLE  \
298         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
299
300 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
301 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
302
303 /* I2C */
304 #define CONFIG_SYS_I2C
305 #define CONFIG_SYS_I2C_FSL
306 #define CONFIG_SYS_FSL_I2C_SPEED        400000
307 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
308 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
309 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
310 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
311 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
312
313 /*
314  * General PCI
315  * Addresses are mapped 1-1.
316  */
317 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
318 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
319 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
320 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
321 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
322 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
323 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
324 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
325 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
326
327 /* enable PCIE clock */
328 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
329
330 #define CONFIG_PCI_INDIRECT_BRIDGE
331 #define CONFIG_PCIE
332
333 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
334 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
335
336 /*
337  * TSEC
338  */
339 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
340 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
341 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
342 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
343 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
344
345 /*
346  * TSEC ethernet configuration
347  */
348 #define CONFIG_MII              1 /* MII PHY management */
349 #define CONFIG_TSEC1_NAME       "eTSEC0"
350 #define CONFIG_TSEC2_NAME       "eTSEC1"
351 #define TSEC1_PHY_ADDR          1
352 #define TSEC2_PHY_ADDR          2
353 #define TSEC1_PHYIDX            0
354 #define TSEC2_PHYIDX            0
355 #define TSEC1_FLAGS             0
356 #define TSEC2_FLAGS             0
357
358 /* Options are: eTSEC[0-1] */
359 #define CONFIG_ETHPRIME         "eTSEC0"
360
361 /*
362  * Environment
363  */
364 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
365                                  CONFIG_SYS_MONITOR_LEN)
366 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
367 #define CONFIG_ENV_SIZE         0x2000
368 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
369 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
370
371 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
372 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
373
374 /*
375  * BOOTP options
376  */
377 #define CONFIG_BOOTP_BOOTFILESIZE
378 #define CONFIG_BOOTP_BOOTPATH
379 #define CONFIG_BOOTP_GATEWAY
380 #define CONFIG_BOOTP_HOSTNAME
381
382 /*
383  * Command line configuration.
384  */
385
386 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
387
388 /*
389  * Miscellaneous configurable options
390  */
391 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
392 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
393
394 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
395
396 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
397 /* Boot Argument Buffer Size */
398 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
399
400 /*
401  * For booting Linux, the board info and command line data
402  * have to be in the first 8 MB of memory, since this is
403  * the maximum mapped by the Linux kernel during initialization.
404  */
405 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
406
407 /*
408  * Core HID Setup
409  */
410 #define CONFIG_SYS_HID0_INIT    0x000000000
411 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
412                                  HID0_ENABLE_INSTRUCTION_CACHE | \
413                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
414 #define CONFIG_SYS_HID2         HID2_HBE
415
416 /*
417  * MMU Setup
418  */
419
420 /* DDR: cache cacheable */
421 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
422                                         BATL_MEMCOHERENCE)
423 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
424                                         BATU_VS | BATU_VP)
425 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
426 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
427
428 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
429 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
430                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
431 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
432                                         BATU_VP)
433 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
434 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
435
436 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
437 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
438                                         BATL_MEMCOHERENCE)
439 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
440                                         BATU_VS | BATU_VP)
441 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
442                                         BATL_CACHEINHIBIT | \
443                                         BATL_GUARDEDSTORAGE)
444 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
445
446 /* Stack in dcache: cacheable, no memory coherence */
447 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
448 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
449                                         BATU_VS | BATU_VP)
450 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
451 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
452
453 /*
454  * Environment Configuration
455  */
456
457 #define CONFIG_ENV_OVERWRITE
458
459 #if defined(CONFIG_TSEC_ENET)
460 #define CONFIG_HAS_ETH0
461 #define CONFIG_HAS_ETH1
462 #endif
463
464 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
465
466
467 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
468         "netdev=eth0\0"                                                 \
469         "consoledev=ttyS0\0"                                            \
470         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
471                 "nfsroot=${serverip}:${rootpath}\0"                     \
472         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
473         "addip=setenv bootargs ${bootargs} "                            \
474                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
475                 ":${hostname}:${netdev}:off panic=1\0"                  \
476         "addtty=setenv bootargs ${bootargs}"                            \
477                 " console=${consoledev},${baudrate}\0"                  \
478         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
479         "addmisc=setenv bootargs ${bootargs}\0"                         \
480         "kernel_addr=FC0A0000\0"                                        \
481         "fdt_addr=FC2A0000\0"                                           \
482         "ramdisk_addr=FC2C0000\0"                                       \
483         "u-boot=mpc8308_p1m/u-boot.bin\0"                               \
484         "kernel_addr_r=1000000\0"                                       \
485         "fdt_addr_r=C00000\0"                                           \
486         "hostname=mpc8308_p1m\0"                                        \
487         "bootfile=mpc8308_p1m/uImage\0"                                 \
488         "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0"                         \
489         "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
490         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
491                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
492         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
493                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
494         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
495                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
496                 "run nfsargs addip addtty addmtd addmisc;"              \
497                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
498         "bootcmd=run flash_self\0"                                      \
499         "load=tftp ${loadaddr} ${u-boot}\0"                             \
500         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
501                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
502                 " +${filesize};cp.b ${fileaddr} "                       \
503                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
504         "upd=run load update\0"                                         \
505
506 #endif  /* __CONFIG_H */