2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
4 * Configuration settings for the MX31ADS Freescale board.
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
14 /* High Level Configuration Options */
15 #define CONFIG_MX31 1 /* This is a mx31 */
17 #define CONFIG_SYS_GENERIC_BOARD
19 #define CONFIG_DISPLAY_CPUINFO
20 #define CONFIG_DISPLAY_BOARDINFO
22 #define CONFIG_SYS_TEXT_BASE 0xA0000000
24 #define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS
27 * Disabled for now due to build problems under Debian and a significant increase
28 * in the final file size: 144260 vs. 109536 Bytes.
31 #define CONFIG_OF_LIBFDT 1
33 #define CONFIG_FIT_VERBOSE 1
36 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
37 #define CONFIG_SETUP_MEMORY_TAGS 1
38 #define CONFIG_INITRD_TAG 1
41 * Size of malloc() pool
43 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
49 #define CONFIG_MXC_UART
50 #define CONFIG_MXC_UART_BASE UART1_BASE
52 #define CONFIG_HARD_SPI 1
53 #define CONFIG_MXC_SPI 1
54 #define CONFIG_DEFAULT_SPI_BUS 1
55 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
56 #define CONFIG_MXC_GPIO
60 #define CONFIG_POWER_SPI
61 #define CONFIG_POWER_FSL
62 #define CONFIG_FSL_PMIC_BUS 1
63 #define CONFIG_FSL_PMIC_CS 0
64 #define CONFIG_FSL_PMIC_CLK 1000000
65 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
66 #define CONFIG_FSL_PMIC_BITLEN 32
67 #define CONFIG_RTC_MC13XXX
69 /* allow to overwrite serial and ethaddr */
70 #define CONFIG_ENV_OVERWRITE
71 #define CONFIG_CONS_INDEX 1
72 #define CONFIG_BAUDRATE 115200
74 /***********************************************************
76 ***********************************************************/
78 #include <config_cmd_default.h>
80 #define CONFIG_CMD_PING
81 #define CONFIG_CMD_DHCP
82 #define CONFIG_CMD_SPI
83 #define CONFIG_CMD_DATE
85 #define CONFIG_BOOTDELAY 3
87 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
89 #define CONFIG_EXTRA_ENV_SETTINGS \
91 "uboot_addr=0xa0000000\0" \
92 "uboot=mx31ads/u-boot.bin\0" \
93 "kernel=mx31ads/uImage\0" \
94 "nfsroot=/opt/eldk/arm\0" \
95 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
96 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
97 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
98 "bootcmd=run bootcmd_net\0" \
99 "bootcmd_net=run bootargs_base bootargs_nfs; " \
100 "tftpboot ${loadaddr} ${kernel}; bootm\0" \
101 "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
102 "protect off ${uboot_addr} 0xa003ffff; " \
103 "erase ${uboot_addr} 0xa003ffff; " \
104 "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
105 "setenv filesize; saveenv\0"
107 #define CONFIG_CS8900
108 #define CONFIG_CS8900_BASE 0xb4020300
109 #define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */
112 * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
113 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
114 * controller inverted. The controller is capable of detecting and correcting
115 * this, but it needs 4 network packets for that. Which means, at startup, you
116 * will not receive answers to the first 4 packest, unless there have been some
117 * broadcasts on the network, or your board is on a hub. Reducing the ARP
118 * timeout from default 5 seconds to 200ms we speed up the initial TFTP
119 * transfer, should the user wish one, significantly.
121 #define CONFIG_ARP_TIMEOUT 200UL
124 * Miscellaneous configurable options
126 #define CONFIG_SYS_LONGHELP /* undef to save memory */
127 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
128 /* Print Buffer Size */
129 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
130 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
131 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
133 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
134 #define CONFIG_SYS_MEMTEST_END 0x10000
136 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
138 #define CONFIG_CMDLINE_EDITING 1
140 /*-----------------------------------------------------------------------
141 * Physical Memory Map
143 #define CONFIG_NR_DRAM_BANKS 1
144 #define PHYS_SDRAM_1 CSD0_BASE
145 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
146 #define CONFIG_BOARD_EARLY_INIT_F
148 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
149 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
150 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
151 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
152 GENERATED_GBL_DATA_SIZE)
153 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
154 CONFIG_SYS_GBL_DATA_OFFSET)
156 /*-----------------------------------------------------------------------
157 * FLASH and environment organization
159 #define CONFIG_SYS_FLASH_BASE CS0_BASE
160 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
161 #define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
162 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
163 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */
165 #define CONFIG_ENV_IS_IN_FLASH 1
166 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
167 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
168 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
170 /* Address and size of Redundant Environment Sector */
171 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
172 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
175 /*-----------------------------------------------------------------------
176 * CFI FLASH driver setup
178 #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
179 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
180 #define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */
181 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
182 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
187 #undef CONFIG_CMD_MTDPARTS
188 #define CONFIG_JFFS2_DEV "nor0"
190 #endif /* __CONFIG_H */