2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
5 * Configuration settings for Freescale MX53 low cost board.
7 * SPDX-License-Identifier: GPL-2.0+
15 #define CONFIG_DISPLAY_BOARDINFO
17 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
19 #include <asm/arch/imx-regs.h>
21 #define CONFIG_CMDLINE_TAG
22 #define CONFIG_SETUP_MEMORY_TAGS
23 #define CONFIG_INITRD_TAG
25 #define CONFIG_SYS_FSL_CLK
27 /* Size of malloc() pool */
28 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
30 #define CONFIG_BOARD_EARLY_INIT_F
31 #define CONFIG_BOARD_LATE_INIT
32 #define CONFIG_MXC_GPIO
33 #define CONFIG_REVISION_TAG
35 #define CONFIG_MXC_UART
36 #define CONFIG_MXC_UART_BASE UART1_BASE
39 #define CONFIG_FSL_ESDHC
40 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
41 #define CONFIG_SYS_FSL_ESDHC_NUM 2
44 #define CONFIG_GENERIC_MMC
45 #define CONFIG_DOS_PARTITION
50 #define CONFIG_FEC_MXC
51 #define IMX_FEC_BASE FEC_BASE_ADDR
52 #define CONFIG_FEC_MXC_PHYADDR 0x1F
55 #define CONFIG_USB_EHCI
56 #define CONFIG_USB_EHCI_MX5
57 #define CONFIG_USB_STORAGE
58 #define CONFIG_USB_HOST_ETHER
59 #define CONFIG_USB_ETHER_ASIX
60 #define CONFIG_USB_ETHER_MCS7830
61 #define CONFIG_USB_ETHER_SMSC95XX
62 #define CONFIG_MXC_USB_PORT 1
63 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
64 #define CONFIG_MXC_USB_FLAGS 0
67 #define CONFIG_SYS_I2C
68 #define CONFIG_SYS_I2C_MXC
69 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
70 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
71 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
75 #define CONFIG_POWER_I2C
76 #define CONFIG_DIALOG_POWER
77 #define CONFIG_POWER_FSL
78 #define CONFIG_POWER_FSL_MC13892
79 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
80 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
82 /* allow to overwrite serial and ethaddr */
83 #define CONFIG_ENV_OVERWRITE
84 #define CONFIG_CONS_INDEX 1
85 #define CONFIG_BAUDRATE 115200
87 /* Command definition */
88 #define CONFIG_SUPPORT_RAW_INITRD
91 #define CONFIG_ETHPRIME "FEC0"
93 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
94 #define CONFIG_SYS_TEXT_BASE 0x77800000
96 #define CONFIG_EXTRA_ENV_SETTINGS \
99 "fdt_addr=0x71000000\0" \
104 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
105 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
107 "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
108 "bootscript=echo Running bootscript from mmc ...; " \
110 "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
111 "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
112 "mmcboot=echo Booting from mmc ...; " \
114 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
115 "if run loadfdt; then " \
116 "bootz ${loadaddr} - ${fdt_addr}; " \
118 "if test ${boot_fdt} = try; then " \
121 "echo WARN: Cannot load the DT; " \
127 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
129 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
130 "netboot=echo Booting from net ...; " \
132 "if test ${ip_dyn} = yes; then " \
133 "setenv get_cmd dhcp; " \
135 "setenv get_cmd tftp; " \
137 "${get_cmd} ${image}; " \
138 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
139 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
140 "bootz ${loadaddr} - ${fdt_addr}; " \
142 "if test ${boot_fdt} = try; then " \
145 "echo ERROR: Cannot load the DT; " \
153 #define CONFIG_BOOTCOMMAND \
154 "mmc dev ${mmcdev}; if mmc rescan; then " \
155 "if run loadbootscript; then " \
158 "if run loadimage; then " \
160 "else run netboot; " \
163 "else run netboot; fi"
165 #define CONFIG_ARP_TIMEOUT 200UL
167 /* Miscellaneous configurable options */
168 #define CONFIG_SYS_LONGHELP /* undef to save memory */
169 #define CONFIG_AUTO_COMPLETE
170 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
172 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
173 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
175 #define CONFIG_SYS_MEMTEST_START 0x70000000
176 #define CONFIG_SYS_MEMTEST_END 0x70010000
178 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
180 #define CONFIG_CMDLINE_EDITING
182 /* Physical Memory Map */
183 #define CONFIG_NR_DRAM_BANKS 2
184 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
185 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
186 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
187 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
188 #define PHYS_SDRAM_SIZE (gd->ram_size)
190 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
191 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
192 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
194 #define CONFIG_SYS_INIT_SP_OFFSET \
195 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
196 #define CONFIG_SYS_INIT_SP_ADDR \
197 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
199 /* FLASH and environment organization */
200 #define CONFIG_SYS_NO_FLASH
202 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
203 #define CONFIG_ENV_SIZE (8 * 1024)
204 #define CONFIG_ENV_IS_IN_MMC
205 #define CONFIG_SYS_MMC_ENV_DEV 0
207 #define CONFIG_CMD_SATA
208 #ifdef CONFIG_CMD_SATA
209 #define CONFIG_DWC_AHSATA
210 #define CONFIG_SYS_SATA_MAX_DEVICE 1
211 #define CONFIG_DWC_AHSATA_PORT_ID 0
212 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
214 #define CONFIG_LIBATA
217 /* Framebuffer and LCD */
218 #define CONFIG_PREBOOT
220 #define CONFIG_VIDEO_IPUV3
221 #define CONFIG_CFB_CONSOLE
222 #define CONFIG_VGA_AS_SINGLE_DEVICE
223 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
224 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
225 #define CONFIG_VIDEO_BMP_RLE8
226 #define CONFIG_SPLASH_SCREEN
227 #define CONFIG_BMP_16BPP
228 #define CONFIG_VIDEO_LOGO
229 #define CONFIG_IPUV3_CLK 200000000
231 #endif /* __CONFIG_H */