2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX6Q Sabre Lite board.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #define CONFIG_SYS_MX6_HCLK 24000000
27 #define CONFIG_SYS_MX6_CLK32 32768
28 #define CONFIG_DISPLAY_CPUINFO
29 #define CONFIG_DISPLAY_BOARDINFO
31 #define CONFIG_MACH_TYPE 3769
33 #include <asm/arch/imx-regs.h>
35 #define CONFIG_CMDLINE_TAG
36 #define CONFIG_SETUP_MEMORY_TAGS
37 #define CONFIG_INITRD_TAG
38 #define CONFIG_REVISION_TAG
40 /* Size of malloc() pool */
41 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
43 #define CONFIG_BOARD_EARLY_INIT_F
44 #define CONFIG_MISC_INIT_R
45 #define CONFIG_MXC_GPIO
47 #define CONFIG_MXC_UART
48 #define CONFIG_MXC_UART_BASE UART2_BASE
52 #define CONFIG_SPI_FLASH
53 #define CONFIG_SPI_FLASH_SST
54 #define CONFIG_MXC_SPI
55 #define CONFIG_SF_DEFAULT_BUS 0
56 #define CONFIG_SF_DEFAULT_CS (0|(GPIO_NUMBER(3, 19)<<8))
57 #define CONFIG_SF_DEFAULT_SPEED 25000000
58 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
62 #define CONFIG_CMD_I2C
63 #define CONFIG_I2C_MULTI_BUS
64 #define CONFIG_I2C_MXC
65 #define CONFIG_SYS_I2C_SPEED 100000
68 #define CONFIG_FSL_ESDHC
69 #define CONFIG_FSL_USDHC
70 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
71 #define CONFIG_SYS_FSL_USDHC_NUM 2
74 #define CONFIG_CMD_MMC
75 #define CONFIG_GENERIC_MMC
76 #define CONFIG_CMD_EXT2
77 #define CONFIG_CMD_FAT
78 #define CONFIG_DOS_PARTITION
80 #define CONFIG_CMD_SATA
84 #ifdef CONFIG_CMD_SATA
85 #define CONFIG_DWC_AHSATA
86 #define CONFIG_SYS_SATA_MAX_DEVICE 1
87 #define CONFIG_DWC_AHSATA_PORT_ID 0
88 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
93 #define CONFIG_CMD_PING
94 #define CONFIG_CMD_DHCP
95 #define CONFIG_CMD_MII
96 #define CONFIG_CMD_NET
97 #define CONFIG_FEC_MXC
99 #define IMX_FEC_BASE ENET_BASE_ADDR
100 #define CONFIG_FEC_XCV_TYPE RGMII
101 #define CONFIG_ETHPRIME "FEC"
102 #define CONFIG_FEC_MXC_PHYADDR 6
103 #define CONFIG_PHYLIB
104 #define CONFIG_PHY_MICREL
105 #define CONFIG_PHY_MICREL_KSZ9021
108 #define CONFIG_CMD_USB
109 #define CONFIG_CMD_FAT
110 #define CONFIG_USB_EHCI
111 #define CONFIG_USB_EHCI_MX6
112 #define CONFIG_USB_STORAGE
113 #define CONFIG_USB_HOST_ETHER
114 #define CONFIG_USB_ETHER_ASIX
115 #define CONFIG_USB_ETHER_SMSC95XX
116 #define CONFIG_MXC_USB_PORT 1
117 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
118 #define CONFIG_MXC_USB_FLAGS 0
120 /* Miscellaneous commands */
121 #define CONFIG_CMD_BMODE
123 /* allow to overwrite serial and ethaddr */
124 #define CONFIG_ENV_OVERWRITE
125 #define CONFIG_CONS_INDEX 1
126 #define CONFIG_BAUDRATE 115200
128 /* Command definition */
129 #include <config_cmd_default.h>
131 #undef CONFIG_CMD_IMLS
133 #define CONFIG_BOOTDELAY 3
135 #define CONFIG_PREBOOT ""
137 #define CONFIG_LOADADDR 0x10800000
138 #define CONFIG_SYS_TEXT_BASE 0x17800000
140 #define CONFIG_EXTRA_ENV_SETTINGS \
141 "script=boot.scr\0" \
143 "console=ttymxc1\0" \
144 "fdt_high=0xffffffff\0" \
145 "initrd_high=0xffffffff\0" \
148 "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
149 "mmcargs=setenv bootargs console=${console},${baudrate} " \
150 "root=${mmcroot}\0" \
152 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
153 "bootscript=echo Running bootscript from mmc ...; " \
155 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
156 "mmcboot=echo Booting from mmc ...; " \
159 "netargs=setenv bootargs console=${console},${baudrate} " \
161 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
162 "netboot=echo Booting from net ...; " \
164 "dhcp ${uimage}; bootm\0" \
166 #define CONFIG_BOOTCOMMAND \
167 "mmc dev ${mmcdev};" \
168 "if mmc rescan ${mmcdev}; then " \
169 "if run loadbootscript; then " \
172 "if run loaduimage; then " \
174 "else run netboot; " \
177 "else run netboot; fi"
179 #define CONFIG_ARP_TIMEOUT 200UL
181 /* Miscellaneous configurable options */
182 #define CONFIG_SYS_LONGHELP
183 #define CONFIG_SYS_HUSH_PARSER
184 #define CONFIG_SYS_PROMPT "MX6QSABRELITE U-Boot > "
185 #define CONFIG_AUTO_COMPLETE
186 #define CONFIG_SYS_CBSIZE 256
188 /* Print Buffer Size */
189 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
190 #define CONFIG_SYS_MAXARGS 16
191 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
193 #define CONFIG_SYS_MEMTEST_START 0x10000000
194 #define CONFIG_SYS_MEMTEST_END 0x10010000
196 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
197 #define CONFIG_SYS_HZ 1000
199 #define CONFIG_CMDLINE_EDITING
201 /* Physical Memory Map */
202 #define CONFIG_NR_DRAM_BANKS 1
203 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
204 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
206 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
207 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
208 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
210 #define CONFIG_SYS_INIT_SP_OFFSET \
211 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
212 #define CONFIG_SYS_INIT_SP_ADDR \
213 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
215 /* FLASH and environment organization */
216 #define CONFIG_SYS_NO_FLASH
218 #define CONFIG_ENV_SIZE (8 * 1024)
220 #define CONFIG_ENV_IS_IN_MMC
221 /* #define CONFIG_ENV_IS_IN_SPI_FLASH */
223 #if defined(CONFIG_ENV_IS_IN_MMC)
224 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
225 #define CONFIG_SYS_MMC_ENV_DEV 0
226 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
227 #define CONFIG_ENV_OFFSET (768 * 1024)
228 #define CONFIG_ENV_SECT_SIZE (8 * 1024)
229 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
230 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
231 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
232 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
235 #define CONFIG_OF_LIBFDT
236 #define CONFIG_CMD_BOOTZ
238 #define CONFIG_SYS_DCACHE_OFF
240 #ifndef CONFIG_SYS_DCACHE_OFF
241 #define CONFIG_CMD_CACHE
244 #endif /* __CONFIG_H */