2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX6SL EVK board.
6 * SPDX-License-Identifier: GPL-2.0+
12 #include "mx6_common.h"
14 #define MACH_TYPE_MX6SLEVK 4307
15 #define CONFIG_MACH_TYPE MACH_TYPE_MX6SLEVK
17 #define CONFIG_CMDLINE_TAG
18 #define CONFIG_SETUP_MEMORY_TAGS
19 #define CONFIG_INITRD_TAG
20 #define CONFIG_REVISION_TAG
22 /* Size of malloc() pool */
23 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
25 #define CONFIG_BOARD_EARLY_INIT_F
26 #define CONFIG_MXC_GPIO
28 #define CONFIG_MXC_UART
29 #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
32 #define CONFIG_FSL_ESDHC
33 #define CONFIG_FSL_USDHC
34 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
37 #define CONFIG_CMD_MMC
38 #define CONFIG_GENERIC_MMC
39 #define CONFIG_CMD_FAT
40 #define CONFIG_DOS_PARTITION
43 #define CONFIG_CMD_I2C
44 #define CONFIG_SYS_I2C
45 #define CONFIG_SYS_I2C_MXC
46 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
47 #define CONFIG_SYS_I2C_SPEED 100000
51 #define CONFIG_POWER_I2C
52 #define CONFIG_POWER_PFUZE100
53 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
55 #define CONFIG_CMD_PING
56 #define CONFIG_CMD_DHCP
57 #define CONFIG_CMD_MII
58 #define CONFIG_CMD_NET
59 #define CONFIG_FEC_MXC
61 #define IMX_FEC_BASE ENET_BASE_ADDR
62 #define CONFIG_FEC_XCV_TYPE RMII
63 #define CONFIG_ETHPRIME "FEC"
64 #define CONFIG_FEC_MXC_PHYADDR 0
67 #define CONFIG_PHY_SMSC
69 /* allow to overwrite serial and ethaddr */
70 #define CONFIG_ENV_OVERWRITE
71 #define CONFIG_CONS_INDEX 1
72 #define CONFIG_BAUDRATE 115200
74 /* Command definition */
76 #define CONFIG_BOOTDELAY 3
78 #define CONFIG_LOADADDR 0x82000000
79 #define CONFIG_SYS_TEXT_BASE 0x87800000
81 #define CONFIG_EXTRA_ENV_SETTINGS \
85 "fdt_high=0xffffffff\0" \
86 "initrd_high=0xffffffff\0" \
87 "fdt_file=imx6sl-evk.dtb\0" \
88 "fdt_addr=0x88000000\0" \
93 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
94 "mmcargs=setenv bootargs console=${console},${baudrate} " \
97 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
98 "bootscript=echo Running bootscript from mmc ...; " \
100 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
101 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
102 "mmcboot=echo Booting from mmc ...; " \
104 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
105 "if run loadfdt; then " \
106 "bootz ${loadaddr} - ${fdt_addr}; " \
108 "if test ${boot_fdt} = try; then " \
111 "echo WARN: Cannot load the DT; " \
117 "netargs=setenv bootargs console=${console},${baudrate} " \
119 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
120 "netboot=echo Booting from net ...; " \
122 "if test ${ip_dyn} = yes; then " \
123 "setenv get_cmd dhcp; " \
125 "setenv get_cmd tftp; " \
127 "${get_cmd} ${image}; " \
128 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
129 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
130 "bootz ${loadaddr} - ${fdt_addr}; " \
132 "if test ${boot_fdt} = try; then " \
135 "echo WARN: Cannot load the DT; " \
142 #define CONFIG_BOOTCOMMAND \
143 "mmc dev ${mmcdev};" \
144 "mmc dev ${mmcdev}; if mmc rescan; then " \
145 "if run loadbootscript; then " \
148 "if run loadimage; then " \
150 "else run netboot; " \
153 "else run netboot; fi"
155 /* Miscellaneous configurable options */
156 #define CONFIG_SYS_LONGHELP
157 #define CONFIG_SYS_HUSH_PARSER
158 #define CONFIG_AUTO_COMPLETE
159 #define CONFIG_SYS_CBSIZE 256
161 #define CONFIG_SYS_MAXARGS 16
162 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
164 #define CONFIG_SYS_MEMTEST_START 0x80000000
165 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M)
167 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
169 #define CONFIG_CMDLINE_EDITING
170 #define CONFIG_STACKSIZE SZ_128K
172 /* Physical Memory Map */
173 #define CONFIG_NR_DRAM_BANKS 1
174 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
175 #define PHYS_SDRAM_SIZE SZ_1G
177 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
178 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
179 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
181 #define CONFIG_SYS_INIT_SP_OFFSET \
182 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
183 #define CONFIG_SYS_INIT_SP_ADDR \
184 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
186 /* Environment organization */
187 #define CONFIG_ENV_SIZE SZ_8K
189 #if defined CONFIG_SYS_BOOT_SPINOR
190 #define CONFIG_ENV_IS_IN_SPI_FLASH
191 #define CONFIG_ENV_OFFSET (768 * 1024)
192 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
193 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
194 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
195 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
196 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
198 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
199 #define CONFIG_ENV_IS_IN_MMC
202 #define CONFIG_OF_LIBFDT
203 #define CONFIG_CMD_BOOTZ
205 #ifndef CONFIG_SYS_DCACHE_OFF
206 #define CONFIG_CMD_CACHE
209 #define CONFIG_CMD_SF
211 #define CONFIG_SPI_FLASH
212 #define CONFIG_SPI_FLASH_STMICRO
213 #define CONFIG_MXC_SPI
214 #define CONFIG_SF_DEFAULT_BUS 0
215 #define CONFIG_SF_DEFAULT_CS 0
216 #define CONFIG_SF_DEFAULT_SPEED 20000000
217 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
221 #define CONFIG_CMD_USB
222 #ifdef CONFIG_CMD_USB
223 #define CONFIG_USB_EHCI
224 #define CONFIG_USB_EHCI_MX6
225 #define CONFIG_USB_STORAGE
226 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
227 #define CONFIG_USB_HOST_ETHER
228 #define CONFIG_USB_ETHER_ASIX
229 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
230 #define CONFIG_MXC_USB_FLAGS 0
231 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
234 #define CONFIG_SYS_FSL_USDHC_NUM 3
235 #if defined(CONFIG_ENV_IS_IN_MMC)
236 #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/
239 #define CONFIG_IMX6_THERMAL
241 #define CONFIG_CMD_FUSE
242 #if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
243 #define CONFIG_MXC_OCOTP
246 #endif /* __CONFIG_H */