2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
7 * Configuration settings for the TI OMAP3530 Beagle board.
9 * SPDX-License-Identifier: GPL-2.0+
15 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
18 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
19 * 64 bytes before this address should be set aside for u-boot.img's
20 * header. That is 0x800FFFC0--0x80100000 should not be used for any
21 * other needs. We use this rather than the inherited defines from
22 * ti_armv7_common.h for backwards compatibility.
24 #define CONFIG_SYS_TEXT_BASE 0x80100000
25 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
26 #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
27 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
28 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
30 #include <configs/ti_omap3_common.h>
33 * Display CPU and Board information
35 #define CONFIG_DISPLAY_CPUINFO 1
36 #define CONFIG_DISPLAY_BOARDINFO 1
38 #define CONFIG_MISC_INIT_R
40 #define CONFIG_REVISION_TAG 1
41 #define CONFIG_ENV_OVERWRITE
44 #define CONFIG_STATUS_LED 1
45 #define CONFIG_BOARD_SPECIFIC_LED 1
46 #define STATUS_LED_BIT 0x01
47 #define STATUS_LED_STATE STATUS_LED_ON
48 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
49 #define STATUS_LED_BIT1 0x02
50 #define STATUS_LED_STATE1 STATUS_LED_ON
51 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
52 #define STATUS_LED_BOOT STATUS_LED_BIT
53 #define STATUS_LED_GREEN STATUS_LED_BIT1
55 /* Enable Multi Bus support for I2C */
56 #define CONFIG_I2C_MULTI_BUS 1
58 /* Probe all devices */
59 #define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}}
62 #define CONFIG_USB_MUSB_OMAP2PLUS
63 #define CONFIG_USB_MUSB_PIO_ONLY
64 #define CONFIG_TWL4030_USB 1
65 #define CONFIG_USB_ETHER
66 #define CONFIG_USB_ETHER_RNDIS
67 #define CONFIG_USB_FUNCTION_FASTBOOT
68 #define CONFIG_CMD_FASTBOOT
69 #define CONFIG_ANDROID_BOOT_IMAGE
70 #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
71 #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
74 #define CONFIG_CMD_USB
75 #define CONFIG_USB_EHCI
77 #define CONFIG_USB_EHCI_OMAP
78 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
80 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
81 #define CONFIG_USB_HOST_ETHER
82 #define CONFIG_USB_ETHER_ASIX
83 #define CONFIG_USB_ETHER_MCS7830
84 #define CONFIG_USB_ETHER_SMSC95XX
87 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
88 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
90 /* commands to include */
91 #define CONFIG_CMD_ASKENV
93 #define CONFIG_CMD_CACHE
95 #define MTDIDS_DEFAULT "nand0=nand"
96 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
97 "1920k(u-boot),128k(u-boot-env),"\
100 #define CONFIG_USB_STORAGE /* USB storage support */
101 #define CONFIG_CMD_NAND /* NAND support */
102 #define CONFIG_CMD_LED /* LED support */
103 #define CONFIG_CMD_DHCP
105 #define CONFIG_VIDEO_OMAP3 /* DSS Support */
110 #define CONFIG_TWL4030_LED 1
115 #define CONFIG_NAND_OMAP_GPMC
116 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
119 #define CONFIG_EXTRA_ENV_SETTINGS \
120 "loadaddr=0x80200000\0" \
121 "rdaddr=0x81000000\0" \
122 "fdt_high=0xffffffff\0" \
123 "fdtaddr=0x80f80000\0" \
125 "bootfile=uImage\0" \
126 "ramdisk=ramdisk.gz\0" \
129 "console=ttyO2,115200n8\0" \
135 "dvimode=640x480MR-16@60\0" \
136 "defaultdisplay=dvi\0" \
138 "mmcroot=/dev/mmcblk0p2 rw\0" \
139 "mmcrootfstype=ext3 rootwait\0" \
140 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
141 "nandrootfstype=ubifs\0" \
142 "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
143 "ramrootfstype=ext2\0" \
144 "mmcargs=setenv bootargs console=${console} " \
146 "mpurate=${mpurate} " \
150 "omapfb.mode=dvi:${dvimode} " \
151 "omapdss.def_disp=${defaultdisplay} " \
153 "rootfstype=${mmcrootfstype}\0" \
154 "nandargs=setenv bootargs console=${console} " \
156 "mpurate=${mpurate} " \
160 "omapfb.mode=dvi:${dvimode} " \
161 "omapdss.def_disp=${defaultdisplay} " \
162 "root=${nandroot} " \
163 "rootfstype=${nandrootfstype}\0" \
165 "if test $beaglerev = AxBx; then " \
166 "setenv fdtfile omap3-beagle.dtb; fi; " \
167 "if test $beaglerev = Cx; then " \
168 "setenv fdtfile omap3-beagle.dtb; fi; " \
169 "if test $beaglerev = C4; then " \
170 "setenv fdtfile omap3-beagle.dtb; fi; " \
171 "if test $beaglerev = xMAB; then " \
172 "setenv fdtfile omap3-beagle-xm-ab.dtb; fi; " \
173 "if test $beaglerev = xMC; then " \
174 "setenv fdtfile omap3-beagle-xm.dtb; fi; " \
175 "if test $fdtfile = undefined; then " \
176 "echo WARNING: Could not determine device tree to use; fi; \0" \
178 "if test $beaglerev = xMAB; then " \
179 "if test ! -e mmc ${bootpart} ${bootdir}/${fdtfile}; then " \
180 "setenv fdtfile omap3-beagle-xm.dtb; " \
183 "bootenv=uEnv.txt\0" \
184 "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
185 "importbootenv=echo Importing environment from mmc ...; " \
186 "env import -t -r $loadaddr $filesize\0" \
187 "ramargs=setenv bootargs console=${console} " \
189 "mpurate=${mpurate} " \
192 "omapfb.mode=dvi:${dvimode} " \
193 "omapdss.def_disp=${defaultdisplay} " \
195 "rootfstype=${ramrootfstype}\0" \
196 "loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
197 "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
198 "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
199 "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
200 "source ${loadaddr}\0" \
201 "loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
202 "mmcboot=echo Booting from mmc ...; " \
204 "bootm ${loadaddr}\0" \
205 "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
207 "bootz ${loadaddr} - ${fdtaddr}\0" \
208 "nandboot=echo Booting from nand ...; " \
210 "nand read ${loadaddr} 280000 400000; " \
211 "bootm ${loadaddr}\0" \
212 "ramboot=echo Booting from ramdisk ...; " \
214 "bootm ${loadaddr}\0" \
215 "userbutton=if gpio input 173; then run userbutton_xm; " \
216 "else run userbutton_nonxm; fi;\0" \
217 "userbutton_xm=gpio input 4;\0" \
218 "userbutton_nonxm=gpio input 7;\0"
219 /* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */
220 #define CONFIG_BOOTCOMMAND \
222 "mmc dev ${mmcdev}; if mmc rescan; then " \
223 "if run userbutton; then " \
224 "setenv bootenv uEnv.txt;" \
226 "setenv bootenv user.txt;" \
228 "echo SD/MMC found on device ${mmcdev};" \
229 "if run loadbootenv; then " \
230 "echo Loaded environment from ${bootenv};" \
231 "run importbootenv;" \
233 "if test -n $uenvcmd; then " \
234 "echo Running uenvcmd ...;" \
237 "if run loadbootscript; then " \
240 "if run loadimage; then " \
246 "setenv bootfile zImage;" \
247 "if run loadimage; then " \
253 * OMAP3 has 12 GP timers, they can be driven by the system clock
254 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
255 * This rate is divided by a local divisor.
257 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
259 /*-----------------------------------------------------------------------
260 * FLASH and environment organization
263 /* **** PISMO SUPPORT *** */
264 #if defined(CONFIG_CMD_NAND)
265 #define CONFIG_SYS_FLASH_BASE NAND_BASE
268 /* Monitor at start of flash */
269 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
270 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
272 #define CONFIG_ENV_IS_IN_NAND 1
273 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
274 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
275 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
277 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
278 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
279 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
281 #define CONFIG_OMAP3_SPI
283 #define CONFIG_SYS_CACHELINE_SIZE 64
285 /* Defines for SPL */
286 #define CONFIG_SPL_OMAP3_ID_NAND
288 /* NAND boot config */
289 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
290 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
291 #define CONFIG_SYS_NAND_PAGE_COUNT 64
292 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
293 #define CONFIG_SYS_NAND_OOBSIZE 64
294 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
295 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
296 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
298 #define CONFIG_SYS_NAND_ECCSIZE 512
299 #define CONFIG_SYS_NAND_ECCBYTES 3
300 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
301 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
302 /* NAND: SPL falcon mode configs */
303 #ifdef CONFIG_SPL_OS_BOOT
304 #define CONFIG_CMD_SPL_NAND_OFS 0x240000
305 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
306 #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
309 #endif /* __CONFIG_H */