2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
7 * Configuration settings for the TI OMAP3530 Beagle board.
9 * SPDX-License-Identifier: GPL-2.0+
16 * High Level Configuration Options
18 #define CONFIG_OMAP 1 /* in a TI OMAP core */
19 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
20 #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
21 #define CONFIG_OMAP_GPIO
22 #define CONFIG_OMAP_COMMON
24 #define CONFIG_SDRC /* The chip has SDRC controller */
26 #include <asm/arch/cpu.h> /* get chip and board defs */
27 #include <asm/arch/omap3.h>
30 * Display CPU and Board information
32 #define CONFIG_DISPLAY_CPUINFO 1
33 #define CONFIG_DISPLAY_BOARDINFO 1
36 #define V_OSCK 26000000 /* Clock output from T2 */
37 #define V_SCLK (V_OSCK >> 1)
39 #define CONFIG_MISC_INIT_R
41 #define CONFIG_OF_LIBFDT
42 #define CONFIG_CMD_BOOTZ
44 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
45 #define CONFIG_SETUP_MEMORY_TAGS 1
46 #define CONFIG_INITRD_TAG 1
47 #define CONFIG_REVISION_TAG 1
50 * Size of malloc() pool
52 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
61 * NS16550 Configuration
63 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
65 #define CONFIG_SYS_NS16550
66 #define CONFIG_SYS_NS16550_SERIAL
67 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
68 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
71 * select serial console configuration
73 #define CONFIG_CONS_INDEX 3
74 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
75 #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
77 /* allow to overwrite serial and ethaddr */
78 #define CONFIG_ENV_OVERWRITE
79 #define CONFIG_BAUDRATE 115200
80 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
82 #define CONFIG_GENERIC_MMC 1
84 #define CONFIG_OMAP_HSMMC 1
85 #define CONFIG_DOS_PARTITION 1
88 #define CONFIG_STATUS_LED 1
89 #define CONFIG_BOARD_SPECIFIC_LED 1
90 #define STATUS_LED_BIT 0x01
91 #define STATUS_LED_STATE STATUS_LED_ON
92 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
93 #define STATUS_LED_BIT1 0x02
94 #define STATUS_LED_STATE1 STATUS_LED_ON
95 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
96 #define STATUS_LED_BOOT STATUS_LED_BIT
97 #define STATUS_LED_GREEN STATUS_LED_BIT1
99 /* Enable Multi Bus support for I2C */
100 #define CONFIG_I2C_MULTI_BUS 1
102 /* Probe all devices */
103 #define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}}
106 #define CONFIG_MUSB_GADGET
107 #define CONFIG_USB_MUSB_OMAP2PLUS
108 #define CONFIG_MUSB_PIO_ONLY
109 #define CONFIG_USB_GADGET_DUALSPEED
110 #define CONFIG_TWL4030_USB 1
111 #define CONFIG_USB_ETHER
112 #define CONFIG_USB_ETHER_RNDIS
113 #define CONFIG_USB_GADGET
114 #define CONFIG_USB_GADGET_VBUS_DRAW 0
115 #define CONFIG_USBDOWNLOAD_GADGET
116 #define CONFIG_G_DNL_VENDOR_NUM 0x0451
117 #define CONFIG_G_DNL_PRODUCT_NUM 0xd022
118 #define CONFIG_G_DNL_MANUFACTURER "TI"
119 #define CONFIG_CMD_FASTBOOT
120 #define CONFIG_ANDROID_BOOT_IMAGE
121 #define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
122 #define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
125 #define CONFIG_CMD_USB
126 #define CONFIG_USB_EHCI
128 #define CONFIG_USB_EHCI_OMAP
129 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
131 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
132 #define CONFIG_USB_HOST_ETHER
133 #define CONFIG_USB_ETHER_ASIX
134 #define CONFIG_USB_ETHER_MCS7830
135 #define CONFIG_USB_ETHER_SMSC95XX
138 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
139 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
141 /* commands to include */
142 #include <config_cmd_default.h>
144 #define CONFIG_CMD_ASKENV
146 #define CONFIG_CMD_CACHE
147 #define CONFIG_CMD_EXT2 /* EXT2 Support */
148 #define CONFIG_CMD_FAT /* FAT support */
149 #define CONFIG_CMD_FS_GENERIC /* Generic FS support */
150 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
151 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
152 #define MTDIDS_DEFAULT "nand0=nand"
153 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
154 "1920k(u-boot),128k(u-boot-env),"\
157 #define CONFIG_CMD_I2C /* I2C serial bus support */
158 #define CONFIG_CMD_MMC /* MMC support */
159 #define CONFIG_USB_STORAGE /* USB storage support */
160 #define CONFIG_CMD_NAND /* NAND support */
161 #define CONFIG_CMD_LED /* LED support */
162 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
163 #define CONFIG_CMD_NFS /* NFS support */
164 #define CONFIG_CMD_PING
165 #define CONFIG_CMD_DHCP
166 #define CONFIG_CMD_SETEXPR /* Evaluate expressions */
167 #define CONFIG_CMD_GPIO /* Enable gpio command */
169 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
170 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
171 #undef CONFIG_CMD_IMI /* iminfo */
172 #undef CONFIG_CMD_IMLS /* List all found images */
174 #define CONFIG_SYS_NO_FLASH
175 #define CONFIG_SYS_I2C
176 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
177 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
178 #define CONFIG_SYS_I2C_OMAP34XX
179 #define CONFIG_VIDEO_OMAP3 /* DSS Support */
184 #define CONFIG_TWL4030_POWER 1
185 #define CONFIG_TWL4030_LED 1
190 #define CONFIG_SYS_NAND_QUIET_TEST 1
191 #define CONFIG_NAND_OMAP_GPMC
192 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
194 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
195 /* to access nand at */
197 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
200 /* Environment information */
201 #define CONFIG_BOOTDELAY 3
203 #define CONFIG_EXTRA_ENV_SETTINGS \
204 "loadaddr=0x80200000\0" \
205 "rdaddr=0x81000000\0" \
206 "fdt_high=0xffffffff\0" \
207 "fdtaddr=0x80f80000\0" \
209 "bootfile=uImage\0" \
210 "ramdisk=ramdisk.gz\0" \
213 "console=ttyO2,115200n8\0" \
219 "dvimode=640x480MR-16@60\0" \
220 "defaultdisplay=dvi\0" \
222 "mmcroot=/dev/mmcblk0p2 rw\0" \
223 "mmcrootfstype=ext3 rootwait\0" \
224 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
225 "nandrootfstype=ubifs\0" \
226 "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
227 "ramrootfstype=ext2\0" \
228 "mmcargs=setenv bootargs console=${console} " \
230 "mpurate=${mpurate} " \
234 "omapfb.mode=dvi:${dvimode} " \
235 "omapdss.def_disp=${defaultdisplay} " \
237 "rootfstype=${mmcrootfstype}\0" \
238 "nandargs=setenv bootargs console=${console} " \
240 "mpurate=${mpurate} " \
244 "omapfb.mode=dvi:${dvimode} " \
245 "omapdss.def_disp=${defaultdisplay} " \
246 "root=${nandroot} " \
247 "rootfstype=${nandrootfstype}\0" \
249 "if test $beaglerev = AxBx; then " \
250 "setenv fdtfile omap3-beagle.dtb; fi; " \
251 "if test $beaglerev = Cx; then " \
252 "setenv fdtfile omap3-beagle.dtb; fi; " \
253 "if test $beaglerev = C4; then " \
254 "setenv fdtfile omap3-beagle.dtb; fi; " \
255 "if test $beaglerev = xMAB; then " \
256 "setenv fdtfile omap3-beagle-xm.dtb; fi; " \
257 "if test $beaglerev = xMC; then " \
258 "setenv fdtfile omap3-beagle-xm.dtb; fi; " \
259 "if test $fdtfile = undefined; then " \
260 "echo WARNING: Could not determine device tree to use; fi; \0" \
261 "bootenv=uEnv.txt\0" \
262 "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
263 "importbootenv=echo Importing environment from mmc ...; " \
264 "env import -t $loadaddr $filesize\0" \
265 "ramargs=setenv bootargs console=${console} " \
267 "mpurate=${mpurate} " \
270 "omapfb.mode=dvi:${dvimode} " \
271 "omapdss.def_disp=${defaultdisplay} " \
273 "rootfstype=${ramrootfstype}\0" \
274 "loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
275 "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
276 "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
277 "mmcboot=echo Booting from mmc ...; " \
279 "bootm ${loadaddr}\0" \
280 "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
282 "bootz ${loadaddr} - ${fdtaddr}\0" \
283 "nandboot=echo Booting from nand ...; " \
285 "nand read ${loadaddr} 280000 400000; " \
286 "bootm ${loadaddr}\0" \
287 "ramboot=echo Booting from ramdisk ...; " \
289 "bootm ${loadaddr}\0" \
290 "userbutton=if gpio input 173; then run userbutton_xm; " \
291 "else run userbutton_nonxm; fi;\0" \
292 "userbutton_xm=gpio input 4;\0" \
293 "userbutton_nonxm=gpio input 7;\0"
294 /* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */
295 #define CONFIG_BOOTCOMMAND \
297 "mmc dev ${mmcdev}; if mmc rescan; then " \
298 "if run userbutton; then " \
299 "setenv bootenv uEnv.txt;" \
301 "setenv bootenv user.txt;" \
303 "echo SD/MMC found on device ${mmcdev};" \
304 "if run loadbootenv; then " \
305 "echo Loaded environment from ${bootenv};" \
306 "run importbootenv;" \
308 "if test -n $uenvcmd; then " \
309 "echo Running uenvcmd ...;" \
312 "if run loadimage; then " \
317 "setenv bootfile zImage;" \
318 "if run loadimage; then " \
323 #define CONFIG_AUTO_COMPLETE 1
325 * Miscellaneous configurable options
327 #define CONFIG_SYS_LONGHELP /* undef to save memory */
328 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
329 #define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
330 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
331 /* Print Buffer Size */
332 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
333 sizeof(CONFIG_SYS_PROMPT) + 16)
334 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
335 /* Boot Argument Buffer Size */
336 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
338 #define CONFIG_SYS_ALT_MEMTEST 1
339 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
341 #define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */
342 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
344 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
348 * OMAP3 has 12 GP timers, they can be driven by the system clock
349 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
350 * This rate is divided by a local divisor.
352 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
353 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
355 /*-----------------------------------------------------------------------
356 * Physical Memory Map
358 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
359 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
360 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
362 /*-----------------------------------------------------------------------
363 * FLASH and environment organization
366 /* **** PISMO SUPPORT *** */
368 /* Configure the PISMO */
369 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
370 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
372 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
374 #if defined(CONFIG_CMD_NAND)
375 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
378 /* Monitor at start of flash */
379 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
380 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
382 #define CONFIG_ENV_IS_IN_NAND 1
383 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
384 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
386 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
387 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
388 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
390 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
391 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
392 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
393 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
394 CONFIG_SYS_INIT_RAM_SIZE - \
395 GENERATED_GBL_DATA_SIZE)
397 #define CONFIG_OMAP3_SPI
399 #define CONFIG_SYS_CACHELINE_SIZE 64
401 /* Defines for SPL */
403 #define CONFIG_SPL_FRAMEWORK
404 #define CONFIG_SPL_NAND_SIMPLE
405 #define CONFIG_SPL_TEXT_BASE 0x40200800
406 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
407 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
409 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
410 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
412 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
413 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
414 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
415 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
417 #define CONFIG_SPL_BOARD_INIT
418 #define CONFIG_SPL_LIBCOMMON_SUPPORT
419 #define CONFIG_SPL_LIBDISK_SUPPORT
420 #define CONFIG_SPL_I2C_SUPPORT
421 #define CONFIG_SPL_LIBGENERIC_SUPPORT
422 #define CONFIG_SPL_MMC_SUPPORT
423 #define CONFIG_SPL_FAT_SUPPORT
424 #define CONFIG_SPL_SERIAL_SUPPORT
425 #define CONFIG_SPL_NAND_SUPPORT
426 #define CONFIG_SPL_NAND_BASE
427 #define CONFIG_SPL_NAND_DRIVERS
428 #define CONFIG_SPL_NAND_ECC
429 #define CONFIG_SPL_GPIO_SUPPORT
430 #define CONFIG_SPL_POWER_SUPPORT
431 #define CONFIG_SPL_OMAP3_ID_NAND
432 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
434 /* NAND boot config */
435 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
436 #define CONFIG_SYS_NAND_PAGE_COUNT 64
437 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
438 #define CONFIG_SYS_NAND_OOBSIZE 64
439 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
440 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
441 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
443 #define CONFIG_SYS_NAND_ECCSIZE 512
444 #define CONFIG_SYS_NAND_ECCBYTES 3
445 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
446 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
447 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
450 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
451 * 64 bytes before this address should be set aside for u-boot.img's
452 * header. That is 0x800FFFC0--0x80100000 should not be used for any
455 #define CONFIG_SYS_TEXT_BASE 0x80100000
456 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
457 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
459 #endif /* __CONFIG_H */