2 * Configuration settings for the TI OMAP3 EVM board.
4 * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
7 * Manikandan Pillai <mani.pillai@ti.com>
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * Manikandan Pillai <mani.pillai@ti.com>
14 * SPDX-License-Identifier: GPL-2.0+
17 #ifndef __OMAP3EVM_CONFIG_H
18 #define __OMAP3EVM_CONFIG_H
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/omap.h>
23 /* ----------------------------------------------------------------------------
24 * Supported U-Boot commands
25 * ----------------------------------------------------------------------------
28 #define CONFIG_CMD_JFFS2
30 #define CONFIG_CMD_NAND
32 /* ----------------------------------------------------------------------------
33 * Supported U-Boot features
34 * ----------------------------------------------------------------------------
36 #define CONFIG_SYS_LONGHELP
38 /* Display CPU and Board information */
39 #define CONFIG_DISPLAY_CPUINFO
40 #define CONFIG_DISPLAY_BOARDINFO
42 /* Allow to overwrite serial and ethaddr */
43 #define CONFIG_ENV_OVERWRITE
45 /* Add auto-completion support */
46 #define CONFIG_AUTO_COMPLETE
48 /* ----------------------------------------------------------------------------
50 * ----------------------------------------------------------------------------
55 #define CONFIG_GENERIC_MMC
56 #define CONFIG_OMAP_HSMMC
59 #define CONFIG_SPL_MMC_SUPPORT
60 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
61 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
62 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
63 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
65 /* Partition tables */
66 #define CONFIG_EFI_PARTITION
67 #define CONFIG_DOS_PARTITION
71 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
72 * Enable CONFIG_USB_MUSB_UDD for Device functionalities.
74 #define CONFIG_USB_OMAP3
75 #define CONFIG_USB_MUSB_HCD
76 /* #define CONFIG_USB_MUSB_UDC */
79 #define CONFIG_SPL_NAND_SIMPLE
80 #define CONFIG_SPL_NAND_SUPPORT
81 #define CONFIG_SPL_NAND_BASE
82 #define CONFIG_SPL_NAND_DRIVERS
83 #define CONFIG_SPL_NAND_ECC
84 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
85 #define CONFIG_SYS_NAND_PAGE_COUNT 64
86 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
87 #define CONFIG_SYS_NAND_OOBSIZE 64
88 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
89 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
90 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
92 #define CONFIG_SYS_NAND_ECCSIZE 512
93 #define CONFIG_SYS_NAND_ECCBYTES 3
94 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
95 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
96 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
99 * High level configuration options
101 #define CONFIG_OMAP /* This is TI OMAP core */
102 #define CONFIG_OMAP_GPIO
103 #define CONFIG_OMAP_COMMON
104 /* Common ARM Erratas */
105 #define CONFIG_ARM_ERRATA_454179
106 #define CONFIG_ARM_ERRATA_430973
107 #define CONFIG_ARM_ERRATA_621766
109 #define CONFIG_SDRC /* The chip has SDRC controller */
111 #define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
112 #define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
115 * Clock related definitions
117 #define V_OSCK 26000000 /* Clock output from T2 */
118 #define V_SCLK (V_OSCK >> 1)
121 * OMAP3 has 12 GP timers, they can be driven by the system clock
122 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
123 * This rate is divided by a local divisor.
125 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
126 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
128 /* Size of environment - 128KB */
129 #define CONFIG_ENV_SIZE (128 << 10)
131 /* Size of malloc pool */
132 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
135 * Physical Memory Map
136 * Note 1: CS1 may or may not be populated
137 * Note 2: SDRAM size is expected to be at least 32MB
139 #define CONFIG_NR_DRAM_BANKS 2
140 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
141 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
143 /* Limits for memtest */
144 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
145 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
146 0x01F00000) /* 31MB */
148 /* Default load address */
149 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
151 /* -----------------------------------------------------------------------------
153 * -----------------------------------------------------------------------------
157 * NS16550 Configuration
159 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
161 #define CONFIG_SYS_NS16550_SERIAL
162 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
163 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
166 * select serial console configuration
168 #define CONFIG_CONS_INDEX 1
169 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
170 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
171 #define CONFIG_BAUDRATE 115200
172 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
178 #define CONFIG_SYS_I2C
179 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
180 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
181 #define CONFIG_SYS_I2C_OMAP34XX
186 /* Monitor at start of flash - Reserve 2 sectors */
187 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
189 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
191 /* Start location & size of environment */
192 #define ONENAND_ENV_OFFSET 0x260000
193 #define SMNAND_ENV_OFFSET 0x260000
195 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
200 /* Physical address to access NAND */
201 #define CONFIG_SYS_NAND_ADDR NAND_BASE
203 /* Physical address to access NAND at CS0 */
204 #define CONFIG_SYS_NAND_BASE NAND_BASE
206 /* Max number of NAND devices */
207 #define CONFIG_SYS_MAX_NAND_DEVICE 1
208 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
209 /* Timeout values (in ticks) */
210 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
211 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
213 /* Flash banks JFFS2 should use */
214 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
215 CONFIG_SYS_MAX_NAND_DEVICE)
217 #define CONFIG_SYS_JFFS2_MEM_NAND
218 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
219 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
221 #define CONFIG_JFFS2_NAND
222 /* nand device jffs2 lives on */
223 #define CONFIG_JFFS2_DEV "nand0"
224 /* Start of jffs2 partition */
225 #define CONFIG_JFFS2_PART_OFFSET 0x680000
226 /* Size of jffs2 partition */
227 #define CONFIG_JFFS2_PART_SIZE 0xf980000
232 #ifdef CONFIG_USB_OMAP3
234 #ifdef CONFIG_USB_MUSB_HCD
236 #define CONGIG_CMD_STORAGE
238 #ifdef CONFIG_USB_KEYBOARD
239 #define CONFIG_SYS_USB_EVENT_POLL
240 #define CONFIG_PREBOOT "usb start"
241 #endif /* CONFIG_USB_KEYBOARD */
243 #endif /* CONFIG_USB_MUSB_HCD */
245 #ifdef CONFIG_USB_MUSB_UDC
246 /* USB device configuration */
247 #define CONFIG_USB_DEVICE
248 #define CONFIG_USB_TTY
249 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
251 /* Change these to suit your needs */
252 #define CONFIG_USBD_VENDORID 0x0451
253 #define CONFIG_USBD_PRODUCTID 0x5678
254 #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
255 #define CONFIG_USBD_PRODUCT_NAME "EVM"
256 #endif /* CONFIG_USB_MUSB_UDC */
258 #endif /* CONFIG_USB_OMAP3 */
260 /* ----------------------------------------------------------------------------
262 * ----------------------------------------------------------------------------
264 #define CONFIG_SYS_MAXARGS 16 /* max args for a command */
266 #define CONFIG_MISC_INIT_R
268 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
269 #define CONFIG_SETUP_MEMORY_TAGS
270 #define CONFIG_INITRD_TAG
271 #define CONFIG_REVISION_TAG
273 /* Size of Console IO buffer */
274 #define CONFIG_SYS_CBSIZE 512
276 /* Size of print buffer */
277 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
278 sizeof(CONFIG_SYS_PROMPT) + 16)
280 /* Size of bootarg buffer */
281 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
283 #define CONFIG_BOOTFILE "uImage"
288 #if defined(CONFIG_CMD_NAND)
289 #define CONFIG_SYS_FLASH_BASE NAND_BASE
291 #define CONFIG_NAND_OMAP_GPMC
292 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
293 #elif defined(CONFIG_CMD_ONENAND)
294 #define CONFIG_SYS_FLASH_BASE ONENAND_MAP
295 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
298 #if !defined(CONFIG_ENV_IS_NOWHERE)
299 #if defined(CONFIG_CMD_NAND)
300 #define CONFIG_ENV_IS_IN_NAND
301 #elif defined(CONFIG_CMD_ONENAND)
302 #define CONFIG_ENV_IS_IN_ONENAND
303 #define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
305 #endif /* CONFIG_ENV_IS_NOWHERE */
307 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
309 #if defined(CONFIG_CMD_NET)
311 /* Ethernet (SMSC9115 from SMSC9118 family) */
312 #define CONFIG_SMC911X
313 #define CONFIG_SMC911X_32_BIT
314 #define CONFIG_SMC911X_BASE 0x2C000000
317 #define CONFIG_BOOTP_SUBNETMASK 0x00000001
318 #define CONFIG_BOOTP_GATEWAY 0x00000002
319 #define CONFIG_BOOTP_HOSTNAME 0x00000004
320 #define CONFIG_BOOTP_BOOTPATH 0x00000010
322 #endif /* CONFIG_CMD_NET */
324 /* Support for relocation */
325 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
326 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
327 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
328 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
329 CONFIG_SYS_INIT_RAM_SIZE - \
330 GENERATED_GBL_DATA_SIZE)
332 /* -----------------------------------------------------------------------------
334 * -----------------------------------------------------------------------------
336 #define CONFIG_SYS_NO_FLASH
338 /* Uncomment to define the board revision statically */
339 /* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
341 /* Defines for SPL */
342 #define CONFIG_SPL_FRAMEWORK
343 #define CONFIG_SPL_TEXT_BASE 0x40200800
344 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
345 CONFIG_SPL_TEXT_BASE)
347 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
348 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
350 #define CONFIG_SPL_BOARD_INIT
351 #define CONFIG_SPL_LIBGENERIC_SUPPORT
352 #define CONFIG_SPL_SERIAL_SUPPORT
353 #define CONFIG_SPL_POWER_SUPPORT
354 #define CONFIG_SPL_OMAP3_ID_NAND
355 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
358 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
359 * 64 bytes before this address should be set aside for u-boot.img's
360 * header. That is 0x800FFFC0--0x80100000 should not be used for any
363 #define CONFIG_SYS_TEXT_BASE 0x80100000
364 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
365 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
367 /* -----------------------------------------------------------------------------
368 * Default environment
369 * -----------------------------------------------------------------------------
372 #define CONFIG_EXTRA_ENV_SETTINGS \
373 "loadaddr=0x82000000\0" \
376 "console=ttyO0,115200n8\0" \
377 "mmcargs=setenv bootargs console=${console} " \
378 "root=/dev/mmcblk0p2 rw " \
379 "rootfstype=ext3 rootwait\0" \
380 "nandargs=setenv bootargs console=${console} " \
381 "root=/dev/mtdblock4 rw " \
382 "rootfstype=jffs2\0" \
383 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
384 "bootscript=echo Running bootscript from mmc ...; " \
385 "source ${loadaddr}\0" \
386 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
387 "mmcboot=echo Booting from mmc ...; " \
389 "bootm ${loadaddr}\0" \
390 "nandboot=echo Booting from nand ...; " \
392 "onenand read ${loadaddr} 280000 400000; " \
393 "bootm ${loadaddr}\0" \
395 #define CONFIG_BOOTCOMMAND \
396 "mmc dev ${mmcdev}; if mmc rescan; then " \
397 "if run loadbootscript; then " \
400 "if run loaduimage; then " \
402 "else run nandboot; " \
405 "else run nandboot; fi"
407 #endif /* __OMAP3EVM_CONFIG_H */