2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * Nishanth Menon <nm@ti.com>
8 * Configuration settings for the TI OMAP3430 Zoom MDK board.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/sizes.h>
34 * High Level Configuration Options
36 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
37 #define CONFIG_OMAP 1 /* in a TI OMAP core */
38 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
39 #define CONFIG_OMAP3430 1 /* which is in a 3430 */
40 #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
42 #include <asm/arch/cpu.h> /* get chip and board defs */
43 #include <asm/arch/omap3.h>
46 * Display CPU and Board information
48 #define CONFIG_DISPLAY_CPUINFO 1
49 #define CONFIG_DISPLAY_BOARDINFO 1
52 #define V_OSCK 26000000 /* Clock output from T2 */
53 #define V_SCLK (V_OSCK >> 1)
55 #undef CONFIG_USE_IRQ /* no support for IRQs */
56 #define CONFIG_MISC_INIT_R
58 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
59 #define CONFIG_SETUP_MEMORY_TAGS 1
60 #define CONFIG_INITRD_TAG 1
61 #define CONFIG_REVISION_TAG 1
64 * Size of malloc() pool
66 #define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
68 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
69 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
77 * NS16550 Configuration
79 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
81 #define CONFIG_SYS_NS16550
82 #define CONFIG_SYS_NS16550_SERIAL
83 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
84 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
87 * select serial console configuration
89 #define CONFIG_CONS_INDEX 3
90 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
91 #define CONFIG_SERIAL3 3 /* UART3 */
93 /* allow to overwrite serial and ethaddr */
94 #define CONFIG_ENV_OVERWRITE
95 #define CONFIG_BAUDRATE 115200
96 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
99 #define CONFIG_OMAP3_MMC 1
100 #define CONFIG_DOS_PARTITION 1
102 /* commands to include */
103 #include <config_cmd_default.h>
105 #define CONFIG_CMD_EXT2 /* EXT2 Support */
106 #define CONFIG_CMD_FAT /* FAT support */
107 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
109 #define CONFIG_CMD_I2C /* I2C serial bus support */
110 #define CONFIG_CMD_MMC /* MMC support */
111 #define CONFIG_CMD_NAND /* NAND support */
112 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
114 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
115 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
116 #undef CONFIG_CMD_IMI /* iminfo */
117 #undef CONFIG_CMD_IMLS /* List all found images */
118 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
119 #undef CONFIG_CMD_NFS /* NFS support */
121 #define CONFIG_SYS_NO_FLASH
122 #define CONFIG_HARD_I2C 1
123 #define CONFIG_SYS_I2C_SPEED 100000
124 #define CONFIG_SYS_I2C_SLAVE 1
125 #define CONFIG_SYS_I2C_BUS 0
126 #define CONFIG_SYS_I2C_BUS_SELECT 1
127 #define CONFIG_DRIVER_OMAP34XX_I2C 1
132 #define CONFIG_TWL4030_POWER 1
133 #define CONFIG_TWL4030_LED 1
138 #define CONFIG_NAND_OMAP_GPMC
139 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
141 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
142 /* to access nand at */
144 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
146 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
149 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
151 #define CONFIG_JFFS2_NAND
152 /* nand device jffs2 lives on */
153 #define CONFIG_JFFS2_DEV "nand0"
154 /* start of jffs2 partition */
155 #define CONFIG_JFFS2_PART_OFFSET 0x680000
156 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
159 /* Environment information */
160 #define CONFIG_BOOTDELAY 10
162 #define CONFIG_EXTRA_ENV_SETTINGS \
163 "loadaddr=0x82000000\0" \
164 "console=ttyS2,115200n8\0" \
165 "videomode=1024x768@60,vxres=1024,vyres=768\0" \
166 "videospec=omapfb:vram:2M,vram:4M\0" \
167 "mmcargs=setenv bootargs console=${console} " \
168 "video=${videospec},mode:${videomode} " \
169 "root=/dev/mmcblk0p2 rw " \
170 "rootfstype=ext3 rootwait\0" \
171 "nandargs=setenv bootargs console=${console} " \
172 "video=${videospec},mode:${videomode} " \
173 "root=/dev/mtdblock4 rw " \
174 "rootfstype=jffs2\0" \
175 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
176 "bootscript=echo Running bootscript from mmc ...; " \
177 "source ${loadaddr}\0" \
178 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
179 "mmcboot=echo Booting from mmc ...; " \
181 "bootm ${loadaddr}\0" \
182 "nandboot=echo Booting from nand ...; " \
184 "nand read ${loadaddr} 280000 400000; " \
185 "bootm ${loadaddr}\0" \
187 #define CONFIG_BOOTCOMMAND \
188 "if mmc init; then " \
189 "if run loadbootscript; then " \
192 "if run loaduimage; then " \
194 "else run nandboot; " \
197 "else run nandboot; fi"
199 #define CONFIG_AUTO_COMPLETE 1
201 * Miscellaneous configurable options
203 #define V_PROMPT "OMAP3 Zoom1# "
205 #define CONFIG_SYS_LONGHELP /* undef to save memory */
206 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
207 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
208 #define CONFIG_SYS_PROMPT V_PROMPT
209 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
210 /* Print Buffer Size */
211 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
212 sizeof(CONFIG_SYS_PROMPT) + 16)
213 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
214 /* Boot Argument Buffer Size */
215 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
217 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
219 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
220 0x01F00000) /* 31MB */
222 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
226 * OMAP3 has 12 GP timers, they can be driven by the system clock
227 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
228 * This rate is divided by a local divisor.
230 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
231 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
232 #define CONFIG_SYS_HZ 1000
234 /*-----------------------------------------------------------------------
237 * The stack sizes are set up in start.S using the settings below
239 #define CONFIG_STACKSIZE SZ_128K /* regular stack */
240 #ifdef CONFIG_USE_IRQ
241 #define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
242 #define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
245 /*-----------------------------------------------------------------------
246 * Physical Memory Map
248 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
249 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
250 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
251 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
253 /* SDRAM Bank Allocation method */
256 /*-----------------------------------------------------------------------
257 * FLASH and environment organization
260 /* **** PISMO SUPPORT *** */
262 /* Configure the PISMO */
263 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
264 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
266 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
268 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
269 #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
271 #define CONFIG_SYS_FLASH_BASE boot_flash_base
273 /* Monitor at start of flash */
274 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
275 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
277 #define CONFIG_ENV_IS_IN_NAND 1
278 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
279 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
281 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
282 #define CONFIG_ENV_OFFSET boot_flash_off
283 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
285 /*-----------------------------------------------------------------------
286 * CFI FLASH driver setup
288 /* timeout values are in ticks */
289 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
290 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
292 /* Flash banks JFFS2 should use */
293 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
294 CONFIG_SYS_MAX_NAND_DEVICE)
295 #define CONFIG_SYS_JFFS2_MEM_NAND
296 /* use flash_info[2] */
297 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
298 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
301 extern struct gpmc *gpmc_cfg;
302 extern unsigned int boot_flash_base;
303 extern volatile unsigned int boot_flash_env_addr;
304 extern unsigned int boot_flash_off;
305 extern unsigned int boot_flash_sec;
306 extern unsigned int boot_flash_type;
309 #endif /* __CONFIG_H */