2 * (C) Copyright 2006-2009
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * Nishanth Menon <nm@ti.com>
7 * Tom Rix <Tom.Rix@windriver.com>
9 * Configuration settings for the TI OMAP3430 Zoom II board.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/sizes.h>
35 * High Level Configuration Options
37 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
38 #define CONFIG_OMAP 1 /* in a TI OMAP core */
39 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
40 #define CONFIG_OMAP3430 1 /* which is in a 3430 */
41 #define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */
43 #include <asm/arch/cpu.h> /* get chip and board defs */
44 #include <asm/arch/omap3.h>
47 * Display CPU and Board information
49 #define CONFIG_DISPLAY_CPUINFO 1
50 #define CONFIG_DISPLAY_BOARDINFO 1
53 #define V_OSCK 26000000 /* Clock output from T2 */
54 #define V_SCLK (V_OSCK >> 1)
56 #undef CONFIG_USE_IRQ /* no support for IRQs */
57 #define CONFIG_MISC_INIT_R
59 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
60 #define CONFIG_SETUP_MEMORY_TAGS 1
61 #define CONFIG_INITRD_TAG 1
62 #define CONFIG_REVISION_TAG 1
65 * Size of malloc() pool
67 #define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
69 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
70 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
77 * NS16550 Configuration
78 * Zoom2 uses the TL16CP754C on the debug board
80 #define CONFIG_SERIAL_MULTI 1
82 * 0 - 1 : first USB with respect to the left edge of the debug board
83 * 2 - 3 : second USB with respect to the left edge of the debug board
85 #define ZOOM2_DEFAULT_SERIAL_DEVICE (&zoom2_serial_device0)
87 #define V_NS16550_CLK (1843200) /* 1.8432 Mhz */
89 #define CONFIG_SYS_NS16550
90 #define CONFIG_SYS_NS16550_REG_SIZE (-2)
91 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
92 #define CONFIG_BAUDRATE 115200
93 #define CONFIG_SYS_BAUDRATE_TABLE {115200}
95 /* allow to overwrite serial and ethaddr */
96 #define CONFIG_ENV_OVERWRITE
99 #define CONFIG_OMAP3_MMC 1
100 #define CONFIG_DOS_PARTITION 1
103 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
104 #define CONFIG_BOARD_SPECIFIC_LED 1
105 #define STATUS_LED_BLUE 0
106 #define STATUS_LED_RED 1
108 #define STATUS_LED_BIT STATUS_LED_BLUE
109 #define STATUS_LED_STATE STATUS_LED_ON
110 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
112 #define STATUS_LED_BIT1 STATUS_LED_RED
113 #define STATUS_LED_STATE1 STATUS_LED_OFF
114 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
116 #define STATUS_LED_BOOT STATUS_LED_BIT
118 /* commands to include */
119 #include <config_cmd_default.h>
121 #define CONFIG_CMD_FAT /* FAT support */
122 #define CONFIG_CMD_I2C /* I2C serial bus support */
123 #define CONFIG_CMD_MMC /* MMC support */
124 #define CONFIG_CMD_NAND /* NAND support */
125 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
127 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
128 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
129 #undef CONFIG_CMD_IMI /* iminfo */
130 #undef CONFIG_CMD_IMLS /* List all found images */
131 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
132 #undef CONFIG_CMD_NFS /* NFS support */
134 #define CONFIG_SYS_NO_FLASH
135 #define CONFIG_SYS_I2C_SPEED 100000
136 #define CONFIG_SYS_I2C_SLAVE 1
137 #define CONFIG_SYS_I2C_BUS 0
138 #define CONFIG_SYS_I2C_BUS_SELECT 1
139 #define CONFIG_DRIVER_OMAP34XX_I2C 1
144 #define CONFIG_NAND_OMAP_GPMC
145 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
147 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
148 /* to access nand at */
150 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
151 #define CONFIG_SYS_MAX_NAND_DEVICE 1
153 /* Environment information */
154 #define CONFIG_BOOTDELAY 10
157 * Miscellaneous configurable options
160 #define CONFIG_SYS_PROMPT "OMAP3 Zoom2 # "
161 #define CONFIG_SYS_LONGHELP
162 #define CONFIG_SYS_CBSIZE 256
163 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
164 sizeof(CONFIG_SYS_PROMPT) + 16)
165 #define CONFIG_SYS_MAXARGS 16
166 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
167 /* Memtest from start of memory to 31MB */
168 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
169 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000)
170 /* The default load address is the start of memory */
171 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
172 /* everything, incl board info, in Hz */
173 #undef CONFIG_SYS_CLKS_IN_HZ
175 * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
176 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
178 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
179 #define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
180 #define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
182 /*-----------------------------------------------------------------------
185 * The stack sizes are set up in start.S using these settings
187 #define CONFIG_STACKSIZE SZ_128K
188 #ifdef CONFIG_USE_IRQ
189 #define CONFIG_STACKSIZE_IRQ SZ_4K
190 #define CONFIG_STACKSIZE_FIQ SZ_4K
193 /*-----------------------------------------------------------------------
194 * Physical Memory Map
196 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
197 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
198 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
199 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
201 /* SDRAM Bank Allocation method */
204 /*-----------------------------------------------------------------------
205 * FLASH and environment organization
208 /* **** PISMO SUPPORT *** */
210 /* Configure the PISMO */
211 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
212 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
214 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
216 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
217 #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
219 #define CONFIG_SYS_FLASH_BASE boot_flash_base
221 /* Monitor at start of flash */
222 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
224 #define CONFIG_ENV_IS_IN_NAND 1
225 #define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */
227 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
228 #define CONFIG_ENV_OFFSET boot_flash_off
229 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
231 /*-----------------------------------------------------------------------
232 * CFI FLASH driver setup
234 /* timeout values are in ticks */
235 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
236 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
239 extern gpmc_csx_t *nand_cs_base;
240 extern gpmc_t *gpmc_cfg_base;
241 extern unsigned int boot_flash_base;
242 extern volatile unsigned int boot_flash_env_addr;
243 extern unsigned int boot_flash_off;
244 extern unsigned int boot_flash_sec;
245 extern unsigned int boot_flash_type;
248 #endif /* __CONFIG_H */