3 * BRIEF MODULE DESCRIPTION
6 * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
7 * Author: MPC-Data Limited
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 #ifndef __INCLUDED_OMAP730_H
33 #define __INCLUDED_OMAP730_H
35 #include <asm/arch/sizes.h>
40 /***************************************************************************
41 * OMAP730 Configuration Registers
42 **************************************************************************/
44 #define PERSEUS2_MPU_DEV_ID ((unsigned int)(0xFFFE1000))
45 #define PERSEUS2_GSM_DEV_ID0 ((unsigned int)(0xFFFE1000))
46 #define PERSEUS2_GDM_DEV_ID1 ((unsigned int)(0xFFFE1002))
47 #define DSP_CONF ((unsigned int)(0xFFFE1004))
48 #define PERSEUS2_MPU_DIE_ID0 ((unsigned int)(0xFFFE1008))
49 #define GSM_ASIC_CONF ((unsigned int)(0xFFFE1008))
50 #define PERSEUS2_MPU_DIE_ID1 ((unsigned int)(0xFFFE100C))
51 #define PERSEUS2_MODE1 ((unsigned int)(0xFFFE1010))
52 #define PERSEUS2_GSM_DIE_ID0 ((unsigned int)(0xFFFE1010))
53 #define PERSEUS2_GSM_DIE_ID1 ((unsigned int)(0xFFFE1012))
54 #define PERSEUS2_MODE2 ((unsigned int)(0xFFFE1014))
55 #define PERSEUS2_GSM_DIE_ID2 ((unsigned int)(0xFFFE1014))
56 #define PERSEUS2_GSM_DIE_ID3 ((unsigned int)(0xFFFE1016))
57 #define PERSEUS2_ANALOG_CELLS_CONF ((unsigned int)(0xFFFE1018))
58 #define SPECCTL ((unsigned int)(0xFFFE101C))
59 #define SPARE1 ((unsigned int)(0xFFFE1020))
60 #define SPARE2 ((unsigned int)(0xFFFE1024))
61 #define GSM_PBG_IRQ ((unsigned int)(0xFFFE1028))
62 #define DMA_REQ_CONF ((unsigned int)(0xFFFE1030))
63 #define PE_CONF_NO_DUAL ((unsigned int)(0xFFFE1060))
64 #define PERSEUS2_IO_CONF0 ((unsigned int)(0xFFFE1070))
65 #define PERSEUS2_IO_CONF1 ((unsigned int)(0xFFFE1074))
66 #define PERSEUS2_IO_CONF2 ((unsigned int)(0xFFFE1078))
67 #define PERSEUS2_IO_CONF3 ((unsigned int)(0xFFFE107C))
68 #define PERSEUS2_IO_CONF4 ((unsigned int)(0xFFFE1080))
69 #define PERSEUS2_IO_CONF5 ((unsigned int)(0xFFFE1084))
70 #define PERSEUS2_IO_CONF6 ((unsigned int)(0xFFFE1088))
71 #define PERSEUS2_IO_CONF7 ((unsigned int)(0xFFFE108C))
72 #define PERSEUS2_IO_CONF8 ((unsigned int)(0xFFFE1090))
73 #define PERSEUS2_IO_CONF9 ((unsigned int)(0xFFFE1094))
74 #define PERSEUS2_IO_CONF10 ((unsigned int)(0xFFFE1098))
75 #define PERSEUS2_IO_CONF11 ((unsigned int)(0xFFFE109C))
76 #define PERSEUS2_IO_CONF12 ((unsigned int)(0xFFFE10A0))
77 #define PERSEUS2_IO_CONF13 ((unsigned int)(0xFFFE10A4))
78 #define PERSEUS_PCC_CONF_REG ((unsigned int)(0xFFFE10B4))
79 #define BIST_STATUS_INTERNAL ((unsigned int)(0xFFFE10B8))
80 #define BIST_CONTROL ((unsigned int)(0xFFFE10C0))
81 #define BOOT_ROM_REG ((unsigned int)(0xFFFE10C4))
82 #define PRODUCTION_ID_REG ((unsigned int)(0xFFFE10C8))
83 #define BIST_SECROM_SIGNATURE1_INTERNAL ((unsigned int)(0xFFFE10D0))
84 #define BIST_SECROM_SIGNATURE2_INTERNAL ((unsigned int)(0xFFFE10D4))
85 #define BIST_CONTROL_2 ((unsigned int)(0xFFFE10D8))
86 #define DEBUG1 ((unsigned int)(0xFFFE10E0))
87 #define DEBUG2 ((unsigned int)(0xFFFE10E4))
88 #define DEBUG_DMA_IRQ ((unsigned int)(0xFFFE10E8))
93 /***************************************************************************
94 * OMAP730 EMIFS Registers (TRM 2.5.7)
95 **************************************************************************/
97 #define TCMIF_BASE 0xFFFECC00
99 #define EMIFS_LRUREG (TCMIF_BASE + 0x04)
100 #define EMIFS_CONFIG (TCMIF_BASE + 0x0C)
101 #define FLASH_CFG_0 (TCMIF_BASE + 0x10)
102 #define FLASH_CFG_1 (TCMIF_BASE + 0x14)
103 #define FLASH_CFG_2 (TCMIF_BASE + 0x18)
104 #define FLASH_CFG_3 (TCMIF_BASE + 0x1C)
105 #define FL_CFG_DYN_WAIT (TCMIF_BASE + 0x40)
106 #define EMIFS_TIMEOUT1_REG (TCMIF_BASE + 0x28)
107 #define EMIFS_TIMEOUT2_REG (TCMIF_BASE + 0x2C)
108 #define EMIFS_TIMEOUT3_REG (TCMIF_BASE + 0x30)
109 #define EMIFS_ABORT_ADDR (TCMIF_BASE + 0x44)
110 #define EMIFS_ABORT_TYPE (TCMIF_BASE + 0x48)
111 #define EMIFS_ABORT_TOUT (TCMIF_BASE + 0x4C)
112 #define FLASH_ACFG_0_1 (TCMIF_BASE + 0x50)
113 #define FLASH_ACFG_1_1 (TCMIF_BASE + 0x54)
114 #define FLASH_ACFG_2_1 (TCMIF_BASE + 0x58)
115 #define FLASH_ACFG_3_1 (TCMIF_BASE + 0x5C)
119 /***************************************************************************
120 * OMAP730 Interrupt handlers
121 **************************************************************************/
123 #define OMAP_IH1_BASE 0xFFFECB00 /* MPU Level 1 IRQ handler */
124 #define OMAP_IH2_BASE 0xfffe0000
128 /***************************************************************************
131 * There are three general purpose OS timers in the 730 that can be
132 * configured in autoreload or one-shot modes.
133 **************************************************************************/
135 #define OMAP730_32kHz_TIMER_BASE 0xFFFB9000
137 /* 32k Timer Registers */
138 #define TIMER32k_CR 0x08
139 #define TIMER32k_TVR 0x00
140 #define TIMER32k_TCR 0x04
142 /* 32k Timer Control Register definition */
143 #define TIMER32k_TSS (1<<0)
144 #define TIMER32k_TRB (1<<1)
145 #define TIMER32k_INT (1<<2)
146 #define TIMER32k_ARL (1<<3)
148 /* MPU Timer base addresses */
149 #define OMAP730_MPUTIMER_BASE 0xfffec500
150 #define OMAP730_MPUTIMER_OFF 0x00000100
152 #define OMAP730_TIMER1_BASE 0xFFFEC500
153 #define OMAP730_TIMER2_BASE 0xFFFEC600
154 #define OMAP730_TIMER3_BASE 0xFFFEC700
156 /* MPU Timer Register offsets */
157 #define CNTL_TIMER 0x00 /* MPU_CNTL_TIMER */
158 #define LOAD_TIM 0x04 /* MPU_LOAD_TIMER */
159 #define READ_TIM 0x08 /* MPU_READ_TIMER */
161 /* MPU_CNTL_TIMER register bits */
162 #define MPUTIM_FREE (1<<6)
163 #define MPUTIM_CLOCK_ENABLE (1<<5)
164 #define MPUTIM_PTV_MASK (0x7<<PTV_BIT)
165 #define MPUTIM_PTV_BIT 2
166 #define MPUTIM_AR (1<<1)
167 #define MPUTIM_ST (1<<0)
171 /***************************************************************************
174 * The GPIO control is split over 6 register bases in the OMAP730 to allow
175 * access to all the (6 x 32) GPIO pins!
176 **************************************************************************/
178 #define OMAP730_GPIO_BASE_1 0xFFFBC000
179 #define OMAP730_GPIO_BASE_2 0xFFFBC800
180 #define OMAP730_GPIO_BASE_3 0xFFFBD000
181 #define OMAP730_GPIO_BASE_4 0xFFFBD800
182 #define OMAP730_GPIO_BASE_5 0xFFFBE000
183 #define OMAP730_GPIO_BASE_6 0xFFFBE800
185 #define GPIO_DATA_INPUT 0x00
186 #define GPIO_DATA_OUTPUT 0x04
187 #define GPIO_DIRECTION_CONTROL 0x08
188 #define GPIO_INTERRUPT_CONTROL 0x0C
189 #define GPIO_INTERRUPT_MASK 0x10
190 #define GPIO_INTERRUPT_STATUS 0x14
192 #define GPIO_DATA_INPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_INPUT))
193 #define GPIO_DATA_OUTPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_OUTPUT))
194 #define GPIO_DIRECTION_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DIRECTION_CONTROL))
195 #define GPIO_INTERRUPT_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_CONTROL))
196 #define GPIO_INTERRUPT_MASK_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_MASK))
197 #define GPIO_INTERRUPT_STATUS_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_STATUS))
199 #define GPIO_DATA_INPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_INPUT))
200 #define GPIO_DATA_OUTPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_OUTPUT))
201 #define GPIO_DIRECTION_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DIRECTION_CONTROL))
202 #define GPIO_INTERRUPT_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_CONTROL))
203 #define GPIO_INTERRUPT_MASK_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_MASK))
204 #define GPIO_INTERRUPT_STATUS_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_STATUS))
206 #define GPIO_DATA_INPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_INPUT))
207 #define GPIO_DATA_OUTPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT))
208 #define GPIO_DIRECTION_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL))
209 #define GPIO_INTERRUPT_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_CONTROL))
210 #define GPIO_INTERRUPT_MASK_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_MASK))
211 #define GPIO_INTERRUPT_STATUS_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_STATUS))
213 #define GPIO_DATA_INPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_INPUT))
214 #define GPIO_DATA_OUTPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_OUTPUT))
215 #define GPIO_DIRECTION_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DIRECTION_CONTROL))
216 #define GPIO_INTERRUPT_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_CONTROL))
217 #define GPIO_INTERRUPT_MASK_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_MASK))
218 #define GPIO_INTERRUPT_STATUS_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_STATUS))
220 #define GPIO_DATA_INPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_INPUT))
221 #define GPIO_DATA_OUTPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT))
222 #define GPIO_DIRECTION_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL))
223 #define GPIO_INTERRUPT_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_CONTROL))
224 #define GPIO_INTERRUPT_MASK_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_MASK))
225 #define GPIO_INTERRUPT_STATUS_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_STATUS))
227 #define GPIO_DATA_INPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_INPUT))
228 #define GPIO_DATA_OUTPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_OUTPUT))
229 #define GPIO_DIRECTION_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DIRECTION_CONTROL))
230 #define GPIO_INTERRUPT_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_CONTROL))
231 #define GPIO_INTERRUPT_MASK_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK))
232 #define GPIO_INTERRUPT_STATUS_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS))
237 /***************************************************************************
238 * OMAP730 Watchdog timers
239 **************************************************************************/
241 #define WDTIM_BASE 0xFFFEC800
242 #define WDTIM_CONTROL (WDTIM_BASE + 0x00) /* MPU_CNTL_TIMER */
243 #define WDTIM_LOAD (WDTIM_BASE + 0x04) /* MPU_LOAD_TIMER */
244 #define WDTIM_READ (WDTIM_BASE + 0x04) /* MPU_READ_TIMER */
245 #define WDTIM_MODE (WDTIM_BASE + 0x08) /* MPU_TIMER_MODE */
250 /***************************************************************************
251 * OMAP730 Interrupt Registers
252 **************************************************************************/
254 /* Interrupt Register offsets */
258 #define IRQ_SIR_IRQ 0x10
259 #define IRQ_SIR_FIQ 0x14
260 #define IRQ_CONTROL_REG 0x18
261 #define IRQ_ILR0 0x1C /* ILRx == ILR0 + (0x4 * x) */
262 #define IRQ_SIR 0x9C /* a.k.a.IRQ_ISR */
263 #define IRQ_GMIR 0xA0
265 #define REG_IHL1_MIR (OMAP_IH1_BASE + IRQ_MIR)
266 #define REG_IHL2_MIR (OMAP_IH2_BASE + IRQ_MIR)
269 /***************************************************************************
270 * OMAP730 Intersystem Communication Register (TRM 4.5)
271 **************************************************************************/
274 #define ICR_BASE 0xFFFBB800
276 #define M_ICR (ICR_BASE + 0x00)
277 #define G_ICR (ICR_BASE + 0x02)
278 #define M_CTL (ICR_BASE + 0x04)
279 #define G_CTL (ICR_BASE + 0x06)
280 #define PM_BA (ICR_BASE + 0x0A)
281 #define DM_BA (ICR_BASE + 0x0C)
282 #define RM_BA (ICR_BASE + 0x0E)
283 #define SSPI_TAS (ICR_BASE + 0x12)
287 #endif /* ! __INCLUDED_OMAP730_H */