2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * QorIQ RDB boards configuration file
13 #if defined(CONFIG_TARGET_P1020MBG)
14 #define CONFIG_BOARDNAME "P1020MBG-PC"
15 #define CONFIG_VSC7385_ENET
17 #define __SW_BOOT_MASK 0x03
18 #define __SW_BOOT_NOR 0xe4
19 #define __SW_BOOT_SD 0x54
20 #define CONFIG_SYS_L2_SIZE (256 << 10)
23 #if defined(CONFIG_TARGET_P1020UTM)
24 #define CONFIG_BOARDNAME "P1020UTM-PC"
25 #define __SW_BOOT_MASK 0x03
26 #define __SW_BOOT_NOR 0xe0
27 #define __SW_BOOT_SD 0x50
28 #define CONFIG_SYS_L2_SIZE (256 << 10)
31 #if defined(CONFIG_TARGET_P1020RDB_PC)
32 #define CONFIG_BOARDNAME "P1020RDB-PC"
33 #define CONFIG_NAND_FSL_ELBC
34 #define CONFIG_VSC7385_ENET
36 #define __SW_BOOT_MASK 0x03
37 #define __SW_BOOT_NOR 0x5c
38 #define __SW_BOOT_SPI 0x1c
39 #define __SW_BOOT_SD 0x9c
40 #define __SW_BOOT_NAND 0xec
41 #define __SW_BOOT_PCIE 0x6c
42 #define CONFIG_SYS_L2_SIZE (256 << 10)
46 * P1020RDB-PD board has user selectable switches for evaluating different
47 * frequency and boot options for the P1020 device. The table that
48 * follow describe the available options. The front six binary number was in
49 * accordance with SW3[1:6].
50 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
51 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
52 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
53 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
54 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
55 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
56 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
58 #if defined(CONFIG_TARGET_P1020RDB_PD)
59 #define CONFIG_BOARDNAME "P1020RDB-PD"
60 #define CONFIG_NAND_FSL_ELBC
61 #define CONFIG_VSC7385_ENET
63 #define __SW_BOOT_MASK 0x03
64 #define __SW_BOOT_NOR 0x64
65 #define __SW_BOOT_SPI 0x34
66 #define __SW_BOOT_SD 0x24
67 #define __SW_BOOT_NAND 0x44
68 #define __SW_BOOT_PCIE 0x74
69 #define CONFIG_SYS_L2_SIZE (256 << 10)
71 * Dynamic MTD Partition support with mtdparts
73 #define CONFIG_MTD_DEVICE
74 #define CONFIG_MTD_PARTITIONS
75 #define CONFIG_FLASH_CFI_MTD
78 #if defined(CONFIG_TARGET_P1021RDB)
79 #define CONFIG_BOARDNAME "P1021RDB-PC"
80 #define CONFIG_NAND_FSL_ELBC
82 #define CONFIG_VSC7385_ENET
83 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
84 addresses in the LBC */
85 #define __SW_BOOT_MASK 0x03
86 #define __SW_BOOT_NOR 0x5c
87 #define __SW_BOOT_SPI 0x1c
88 #define __SW_BOOT_SD 0x9c
89 #define __SW_BOOT_NAND 0xec
90 #define __SW_BOOT_PCIE 0x6c
91 #define CONFIG_SYS_L2_SIZE (256 << 10)
93 * Dynamic MTD Partition support with mtdparts
95 #define CONFIG_MTD_DEVICE
96 #define CONFIG_MTD_PARTITIONS
97 #define CONFIG_FLASH_CFI_MTD
100 #if defined(CONFIG_TARGET_P1024RDB)
101 #define CONFIG_BOARDNAME "P1024RDB"
102 #define CONFIG_NAND_FSL_ELBC
104 #define __SW_BOOT_MASK 0xf3
105 #define __SW_BOOT_NOR 0x00
106 #define __SW_BOOT_SPI 0x08
107 #define __SW_BOOT_SD 0x04
108 #define __SW_BOOT_NAND 0x0c
109 #define CONFIG_SYS_L2_SIZE (256 << 10)
112 #if defined(CONFIG_TARGET_P1025RDB)
113 #define CONFIG_BOARDNAME "P1025RDB"
114 #define CONFIG_NAND_FSL_ELBC
118 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
119 addresses in the LBC */
120 #define __SW_BOOT_MASK 0xf3
121 #define __SW_BOOT_NOR 0x00
122 #define __SW_BOOT_SPI 0x08
123 #define __SW_BOOT_SD 0x04
124 #define __SW_BOOT_NAND 0x0c
125 #define CONFIG_SYS_L2_SIZE (256 << 10)
128 #if defined(CONFIG_TARGET_P2020RDB)
129 #define CONFIG_BOARDNAME "P2020RDB-PC"
130 #define CONFIG_NAND_FSL_ELBC
131 #define CONFIG_VSC7385_ENET
132 #define __SW_BOOT_MASK 0x03
133 #define __SW_BOOT_NOR 0xc8
134 #define __SW_BOOT_SPI 0x28
135 #define __SW_BOOT_SD 0x68 /* or 0x18 */
136 #define __SW_BOOT_NAND 0xe8
137 #define __SW_BOOT_PCIE 0xa8
138 #define CONFIG_SYS_L2_SIZE (512 << 10)
140 * Dynamic MTD Partition support with mtdparts
142 #define CONFIG_MTD_DEVICE
143 #define CONFIG_MTD_PARTITIONS
144 #define CONFIG_FLASH_CFI_MTD
148 #define CONFIG_SPL_MMC_MINIMAL
149 #define CONFIG_SPL_FLUSH_IMAGE
150 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
151 #define CONFIG_SYS_TEXT_BASE 0x11001000
152 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
153 #define CONFIG_SPL_PAD_TO 0x20000
154 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
155 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
156 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
157 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
158 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
159 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
160 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
161 #define CONFIG_SPL_MMC_BOOT
162 #ifdef CONFIG_SPL_BUILD
163 #define CONFIG_SPL_COMMON_INIT_DDR
167 #ifdef CONFIG_SPIFLASH
168 #define CONFIG_SPL_SPI_FLASH_MINIMAL
169 #define CONFIG_SPL_FLUSH_IMAGE
170 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
171 #define CONFIG_SYS_TEXT_BASE 0x11001000
172 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
173 #define CONFIG_SPL_PAD_TO 0x20000
174 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
175 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
176 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
177 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
178 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
179 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
180 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
181 #define CONFIG_SPL_SPI_BOOT
182 #ifdef CONFIG_SPL_BUILD
183 #define CONFIG_SPL_COMMON_INIT_DDR
188 #ifdef CONFIG_TPL_BUILD
189 #define CONFIG_SPL_NAND_BOOT
190 #define CONFIG_SPL_FLUSH_IMAGE
191 #define CONFIG_SPL_NAND_INIT
192 #define CONFIG_SPL_COMMON_INIT_DDR
193 #define CONFIG_SPL_MAX_SIZE (128 << 10)
194 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
195 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
196 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
197 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
198 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
199 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
200 #elif defined(CONFIG_SPL_BUILD)
201 #define CONFIG_SPL_INIT_MINIMAL
202 #define CONFIG_SPL_FLUSH_IMAGE
203 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
204 #define CONFIG_SPL_TEXT_BASE 0xff800000
205 #define CONFIG_SPL_MAX_SIZE 4096
206 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
207 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
208 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
209 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
210 #endif /* not CONFIG_TPL_BUILD */
212 #define CONFIG_SPL_PAD_TO 0x20000
213 #define CONFIG_TPL_PAD_TO 0x20000
214 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
215 #define CONFIG_SYS_TEXT_BASE 0x11001000
216 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
219 #ifndef CONFIG_SYS_TEXT_BASE
220 #define CONFIG_SYS_TEXT_BASE 0xeff40000
223 #ifndef CONFIG_RESET_VECTOR_ADDRESS
224 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
227 #ifndef CONFIG_SYS_MONITOR_BASE
228 #ifdef CONFIG_SPL_BUILD
229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
237 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
238 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
239 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
240 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
241 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
242 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
244 #define CONFIG_TSEC_ENET /* tsec ethernet support */
245 #define CONFIG_ENV_OVERWRITE
247 #define CONFIG_SATA_SIL
248 #define CONFIG_SYS_SATA_MAX_DEVICE 2
249 #define CONFIG_LIBATA
252 #if defined(CONFIG_TARGET_P2020RDB)
253 #define CONFIG_SYS_CLK_FREQ 100000000
255 #define CONFIG_SYS_CLK_FREQ 66666666
257 #define CONFIG_DDR_CLK_FREQ 66666666
259 #define CONFIG_HWCONFIG
261 * These can be toggled for performance analysis, otherwise use default.
263 #define CONFIG_L2_CACHE
266 #define CONFIG_ENABLE_36BIT_PHYS
268 #ifdef CONFIG_PHYS_64BIT
269 #define CONFIG_ADDR_MAP 1
270 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
273 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
274 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
275 #define CONFIG_PANIC_HANG /* do not reset board on panic */
277 #define CONFIG_SYS_CCSRBAR 0xffe00000
278 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
280 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
282 #ifdef CONFIG_SPL_BUILD
283 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
287 #define CONFIG_SYS_DDR_RAW_TIMING
288 #define CONFIG_DDR_SPD
289 #define CONFIG_SYS_SPD_BUS_NUM 1
290 #define SPD_EEPROM_ADDRESS 0x52
291 #undef CONFIG_FSL_DDR_INTERACTIVE
293 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
294 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
295 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
297 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
298 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
300 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
301 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
302 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
304 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
306 /* Default settings for DDR3 */
307 #ifndef CONFIG_TARGET_P2020RDB
308 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
309 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
310 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
311 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
312 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
313 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
315 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
316 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
317 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
318 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
320 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
321 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
322 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
323 #define CONFIG_SYS_DDR_RCW_1 0x00000000
324 #define CONFIG_SYS_DDR_RCW_2 0x00000000
325 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
326 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
327 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
328 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
330 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
331 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
332 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
333 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
334 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
335 #define CONFIG_SYS_DDR_MODE_1 0x40461520
336 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
337 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
340 #undef CONFIG_CLOCKS_IN_MHZ
345 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
346 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
347 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
348 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
350 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
351 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
352 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
353 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
354 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
355 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
356 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
360 * Local Bus Definitions
362 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
363 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
364 #define CONFIG_SYS_FLASH_BASE 0xec000000
365 #elif defined(CONFIG_TARGET_P1020UTM)
366 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
367 #define CONFIG_SYS_FLASH_BASE 0xee000000
369 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
370 #define CONFIG_SYS_FLASH_BASE 0xef000000
373 #ifdef CONFIG_PHYS_64BIT
374 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
376 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
379 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
382 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
384 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
385 #define CONFIG_SYS_FLASH_QUIET_TEST
386 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
388 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
390 #undef CONFIG_SYS_FLASH_CHECKSUM
391 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
392 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
394 #define CONFIG_FLASH_CFI_DRIVER
395 #define CONFIG_SYS_FLASH_CFI
396 #define CONFIG_SYS_FLASH_EMPTY_INFO
397 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
400 #ifdef CONFIG_NAND_FSL_ELBC
401 #define CONFIG_SYS_NAND_BASE 0xff800000
402 #ifdef CONFIG_PHYS_64BIT
403 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
405 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
408 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
409 #define CONFIG_SYS_MAX_NAND_DEVICE 1
410 #if defined(CONFIG_TARGET_P1020RDB_PD)
411 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
413 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
416 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
417 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
418 | BR_PS_8 /* Port Size = 8 bit */ \
419 | BR_MS_FCM /* MSEL = FCM */ \
421 #if defined(CONFIG_TARGET_P1020RDB_PD)
422 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
423 | OR_FCM_PGS /* Large Page*/ \
431 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
439 #endif /* CONFIG_NAND_FSL_ELBC */
441 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
443 #define CONFIG_SYS_INIT_RAM_LOCK
444 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
445 #ifdef CONFIG_PHYS_64BIT
446 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
448 /* The assembler doesn't like typecast */
449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
450 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
451 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
453 /* Initial L1 address */
454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
458 /* Size of used area in RAM */
459 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
461 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
462 GENERATED_GBL_DATA_SIZE)
463 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
465 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
466 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
468 #define CONFIG_SYS_CPLD_BASE 0xffa00000
469 #ifdef CONFIG_PHYS_64BIT
470 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
472 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
474 /* CPLD config size: 1Mb */
475 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
477 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
479 #define CONFIG_SYS_PMC_BASE 0xff980000
480 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
481 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
483 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
484 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
488 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
489 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
490 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
491 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
493 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
494 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
495 #ifdef CONFIG_NAND_FSL_ELBC
496 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
497 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
500 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
501 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
504 #ifdef CONFIG_VSC7385_ENET
505 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
507 #ifdef CONFIG_PHYS_64BIT
508 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
510 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
513 #define CONFIG_SYS_VSC7385_BR_PRELIM \
514 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
515 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
516 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
517 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
519 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
520 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
522 /* The size of the VSC7385 firmware image */
523 #define CONFIG_VSC7385_IMAGE_SIZE 8192
527 * Config the L2 Cache as L2 SRAM
529 #if defined(CONFIG_SPL_BUILD)
530 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
531 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
532 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
533 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
534 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
535 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
536 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
537 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
538 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
539 #if defined(CONFIG_TARGET_P2020RDB)
540 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
542 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
544 #elif defined(CONFIG_NAND)
545 #ifdef CONFIG_TPL_BUILD
546 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
547 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
548 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
549 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
550 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
551 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
552 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
553 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
555 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
556 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
557 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
558 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
559 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
560 #endif /* CONFIG_TPL_BUILD */
564 /* Serial Port - controlled on board with jumper J8
568 #define CONFIG_CONS_INDEX 1
569 #undef CONFIG_SERIAL_SOFTWARE_FIFO
570 #define CONFIG_SYS_NS16550_SERIAL
571 #define CONFIG_SYS_NS16550_REG_SIZE 1
572 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
573 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
574 #define CONFIG_NS16550_MIN_FUNCTIONS
577 #define CONFIG_SYS_BAUDRATE_TABLE \
578 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
580 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
581 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
584 #define CONFIG_SYS_I2C
585 #define CONFIG_SYS_I2C_FSL
586 #define CONFIG_SYS_FSL_I2C_SPEED 400000
587 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
588 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
589 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
590 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
591 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
592 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
593 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
594 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
599 #undef CONFIG_ID_EEPROM
601 #define CONFIG_RTC_PT7C4338
602 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
603 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
605 /* enable read and write access to EEPROM */
606 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
607 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
608 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
611 * eSPI - Enhanced SPI
613 #define CONFIG_HARD_SPI
615 #if defined(CONFIG_SPI_FLASH)
616 #define CONFIG_SF_DEFAULT_SPEED 10000000
617 #define CONFIG_SF_DEFAULT_MODE 0
620 #if defined(CONFIG_PCI)
623 * Memory space is mapped 1-1, but I/O space must start from 0.
626 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
627 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
628 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
629 #ifdef CONFIG_PHYS_64BIT
630 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
631 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
633 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
634 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
636 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
637 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
638 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
639 #ifdef CONFIG_PHYS_64BIT
640 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
642 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
644 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
646 /* controller 1, Slot 2, tgtid 1, Base address a000 */
647 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
648 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
649 #ifdef CONFIG_PHYS_64BIT
650 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
651 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
653 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
654 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
656 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
657 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
658 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
659 #ifdef CONFIG_PHYS_64BIT
660 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
662 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
664 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
666 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
667 #endif /* CONFIG_PCI */
669 #if defined(CONFIG_TSEC_ENET)
670 #define CONFIG_MII /* MII PHY management */
672 #define CONFIG_TSEC1_NAME "eTSEC1"
674 #define CONFIG_TSEC2_NAME "eTSEC2"
676 #define CONFIG_TSEC3_NAME "eTSEC3"
678 #define TSEC1_PHY_ADDR 2
679 #define TSEC2_PHY_ADDR 0
680 #define TSEC3_PHY_ADDR 1
682 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
683 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
684 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
686 #define TSEC1_PHYIDX 0
687 #define TSEC2_PHYIDX 0
688 #define TSEC3_PHYIDX 0
690 #define CONFIG_ETHPRIME "eTSEC1"
692 #define CONFIG_HAS_ETH0
693 #define CONFIG_HAS_ETH1
694 #define CONFIG_HAS_ETH2
695 #endif /* CONFIG_TSEC_ENET */
698 /* QE microcode/firmware address */
699 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
700 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
701 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
702 #endif /* CONFIG_QE */
704 #ifdef CONFIG_TARGET_P1025RDB
706 * QE UEC ethernet configuration
708 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
710 #undef CONFIG_UEC_ETH
711 #define CONFIG_PHY_MODE_NEED_CHANGE
713 #define CONFIG_UEC_ETH1 /* ETH1 */
714 #define CONFIG_HAS_ETH0
716 #ifdef CONFIG_UEC_ETH1
717 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
718 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
719 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
720 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
721 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
722 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
723 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
724 #endif /* CONFIG_UEC_ETH1 */
726 #define CONFIG_UEC_ETH5 /* ETH5 */
727 #define CONFIG_HAS_ETH1
729 #ifdef CONFIG_UEC_ETH5
730 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
731 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
732 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
733 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
734 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
735 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
736 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
737 #endif /* CONFIG_UEC_ETH5 */
738 #endif /* CONFIG_TARGET_P1025RDB */
743 #ifdef CONFIG_SPIFLASH
744 #define CONFIG_ENV_SPI_BUS 0
745 #define CONFIG_ENV_SPI_CS 0
746 #define CONFIG_ENV_SPI_MAX_HZ 10000000
747 #define CONFIG_ENV_SPI_MODE 0
748 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
749 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
750 #define CONFIG_ENV_SECT_SIZE 0x10000
751 #elif defined(CONFIG_SDCARD)
752 #define CONFIG_FSL_FIXED_MMC_LOCATION
753 #define CONFIG_ENV_SIZE 0x2000
754 #define CONFIG_SYS_MMC_ENV_DEV 0
755 #elif defined(CONFIG_NAND)
756 #ifdef CONFIG_TPL_BUILD
757 #define CONFIG_ENV_SIZE 0x2000
758 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
760 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
762 #define CONFIG_ENV_OFFSET (1024 * 1024)
763 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
764 #elif defined(CONFIG_SYS_RAMBOOT)
765 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
766 #define CONFIG_ENV_SIZE 0x2000
768 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
769 #define CONFIG_ENV_SIZE 0x2000
770 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
773 #define CONFIG_LOADS_ECHO /* echo on for serial download */
774 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
779 #define CONFIG_HAS_FSL_DR_USB
781 #if defined(CONFIG_HAS_FSL_DR_USB)
782 #ifdef CONFIG_USB_EHCI_HCD
783 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
784 #define CONFIG_USB_EHCI_FSL
785 #define CONFIG_EHCI_DESC_BIG_ENDIAN
789 #if defined(CONFIG_TARGET_P1020RDB_PD)
790 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
794 #define CONFIG_FSL_ESDHC
795 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
798 #undef CONFIG_WATCHDOG /* watchdog disabled */
801 * Miscellaneous configurable options
803 #define CONFIG_SYS_LONGHELP /* undef to save memory */
804 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
805 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
808 * For booting Linux, the board info and command line data
809 * have to be in the first 64 MB of memory, since this is
810 * the maximum mapped by the Linux kernel during initialization.
812 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
813 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
815 #if defined(CONFIG_CMD_KGDB)
816 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
820 * Environment Configuration
822 #define CONFIG_HOSTNAME unknown
823 #define CONFIG_ROOTPATH "/opt/nfsroot"
824 #define CONFIG_BOOTFILE "uImage"
825 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
827 /* default location for tftp and bootm */
828 #define CONFIG_LOADADDR 1000000
831 #define __NOR_RST_CMD \
832 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
833 i2c mw 18 3 __SW_BOOT_MASK 1; reset
836 #define __SPI_RST_CMD \
837 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
838 i2c mw 18 3 __SW_BOOT_MASK 1; reset
841 #define __SD_RST_CMD \
842 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
843 i2c mw 18 3 __SW_BOOT_MASK 1; reset
845 #ifdef __SW_BOOT_NAND
846 #define __NAND_RST_CMD \
847 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
848 i2c mw 18 3 __SW_BOOT_MASK 1; reset
850 #ifdef __SW_BOOT_PCIE
851 #define __PCIE_RST_CMD \
852 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
853 i2c mw 18 3 __SW_BOOT_MASK 1; reset
856 #define CONFIG_EXTRA_ENV_SETTINGS \
858 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
859 "loadaddr=1000000\0" \
860 "bootfile=uImage\0" \
861 "tftpflash=tftpboot $loadaddr $uboot; " \
862 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
863 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
864 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
865 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
866 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
867 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
868 "consoledev=ttyS0\0" \
869 "ramdiskaddr=2000000\0" \
870 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
871 "fdtaddr=1e00000\0" \
873 "jffs2nor=mtdblock3\0" \
874 "norbootaddr=ef080000\0" \
875 "norfdtaddr=ef040000\0" \
876 "jffs2nand=mtdblock9\0" \
877 "nandbootaddr=100000\0" \
878 "nandfdtaddr=80000\0" \
879 "ramdisk_size=120000\0" \
880 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
881 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
882 __stringify(__NOR_RST_CMD)"\0" \
883 __stringify(__SPI_RST_CMD)"\0" \
884 __stringify(__SD_RST_CMD)"\0" \
885 __stringify(__NAND_RST_CMD)"\0" \
886 __stringify(__PCIE_RST_CMD)"\0"
888 #define CONFIG_NFSBOOTCOMMAND \
889 "setenv bootargs root=/dev/nfs rw " \
890 "nfsroot=$serverip:$rootpath " \
891 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
892 "console=$consoledev,$baudrate $othbootargs;" \
893 "tftp $loadaddr $bootfile;" \
894 "tftp $fdtaddr $fdtfile;" \
895 "bootm $loadaddr - $fdtaddr"
897 #define CONFIG_HDBOOT \
898 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
899 "console=$consoledev,$baudrate $othbootargs;" \
901 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
902 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
903 "bootm $loadaddr - $fdtaddr"
905 #define CONFIG_USB_FAT_BOOT \
906 "setenv bootargs root=/dev/ram rw " \
907 "console=$consoledev,$baudrate $othbootargs " \
908 "ramdisk_size=$ramdisk_size;" \
910 "fatload usb 0:2 $loadaddr $bootfile;" \
911 "fatload usb 0:2 $fdtaddr $fdtfile;" \
912 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
913 "bootm $loadaddr $ramdiskaddr $fdtaddr"
915 #define CONFIG_USB_EXT2_BOOT \
916 "setenv bootargs root=/dev/ram rw " \
917 "console=$consoledev,$baudrate $othbootargs " \
918 "ramdisk_size=$ramdisk_size;" \
920 "ext2load usb 0:4 $loadaddr $bootfile;" \
921 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
922 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
923 "bootm $loadaddr $ramdiskaddr $fdtaddr"
925 #define CONFIG_NORBOOT \
926 "setenv bootargs root=/dev/$jffs2nor rw " \
927 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
928 "bootm $norbootaddr - $norfdtaddr"
930 #define CONFIG_RAMBOOTCOMMAND \
931 "setenv bootargs root=/dev/ram rw " \
932 "console=$consoledev,$baudrate $othbootargs " \
933 "ramdisk_size=$ramdisk_size;" \
934 "tftp $ramdiskaddr $ramdiskfile;" \
935 "tftp $loadaddr $bootfile;" \
936 "tftp $fdtaddr $fdtfile;" \
937 "bootm $loadaddr $ramdiskaddr $fdtaddr"
939 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
941 #endif /* __CONFIG_H */