3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * This file contains the configuration parameters for the dbau1x00 board.
15 #define CONFIG_PB1X00 1
16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
19 #define CONFIG_SOC_AU1000 1
22 #define CONFIG_SOC_AU1100 1
25 #define CONFIG_SOC_AU1500 1
27 #error "No valid board set"
32 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
34 #define CONFIG_EXTRA_ENV_SETTINGS \
35 "addmisc=setenv bootargs ${bootargs} " \
36 "console=ttyS0,${baudrate} " \
38 "bootfile=/vmlinux.img\0" \
39 "load=tftp 80500000 ${u-boot}\0" \
41 /* Boot from NFS root */
42 #define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm"
45 * Miscellaneous configurable options
48 #define CONFIG_SYS_MALLOC_LEN 128*1024
50 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
52 #define CONFIG_SYS_MIPS_TIMER_FREQ 396000000
54 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
56 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
58 #define CONFIG_SYS_MEMTEST_START 0x80100000
59 #undef CONFIG_SYS_MEMTEST_START
60 #define CONFIG_SYS_MEMTEST_START 0x80200000
61 #define CONFIG_SYS_MEMTEST_END 0x83800000
63 /*-----------------------------------------------------------------------
64 * FLASH and environment organization
66 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
67 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
69 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
70 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
73 #define CONFIG_SYS_MONITOR_LEN (192 << 10)
75 #define CONFIG_SYS_INIT_SP_OFFSET 0x4000000
77 /* We boot from this flash, selected with dip switch */
78 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
80 /* timeout values are in ticks */
81 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
82 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
84 /* Address and size of Primary Environment Sector */
85 #define CONFIG_ENV_ADDR 0xB0030000
86 #define CONFIG_ENV_SIZE 0x10000
88 #define CONFIG_FLASH_16BIT
90 #define CONFIG_NR_DRAM_BANKS 2
92 #define CONFIG_MEMSIZE_IN_BYTES
94 /*---USB -------------------------------------------*/
96 #define CONFIG_USB_OHCI
99 /*---ATA PCMCIA ------------------------------------*/
101 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
102 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
103 #define CONFIG_PCMCIA_SLOT_A
105 #define CONFIG_ATAPI 1
107 /* We run CF in "true ide" mode or a harddrive via pcmcia */
108 #define CONFIG_IDE_PCMCIA 1
110 /* We only support one slot for now */
111 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
112 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
114 #undef CONFIG_IDE_RESET /* reset for ide not supported */
116 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
118 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
120 /* Offset for data I/O */
121 #define CONFIG_SYS_ATA_DATA_OFFSET 8
123 /* Offset for normal register accesses */
124 #define CONFIG_SYS_ATA_REG_OFFSET 0
126 /* Offset for alternate registers */
127 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
134 #define CONFIG_BOOTP_BOOTFILESIZE
137 * Command line configuration.
140 #endif /* __CONFIG_H */