2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Eric Schumann, Phytec Messatechnik GmbH
9 * Jon Smirl <jonsmirl@gmail.com>
11 * SPDX-License-Identifier: GPL-2.0+
17 #define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny"
19 /*-----------------------------------------------------------------------------
20 High Level Configuration Options
22 -----------------------------------------------------------------------------*/
23 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
24 #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
25 #define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
26 /* FEC configuration and IDE */
29 * Valid values for CONFIG_SYS_TEXT_BASE are:
30 * 0xFFF00000 boot high (standard configuration)
32 * 0x00100000 boot from RAM (for testing only)
34 #ifndef CONFIG_SYS_TEXT_BASE
35 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
38 #define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
40 /*-----------------------------------------------------------------------------
41 Serial console configuration
42 -----------------------------------------------------------------------------*/
43 #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */
44 /*define gps port conf. */
45 /* register later on to */
46 /*enable UART function! */
47 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
48 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
51 * Command line configuration.
53 #define CONFIG_CMD_DATE
54 #define CONFIG_CMD_EEPROM
55 #define CONFIG_CMD_JFFS2
56 #define CONFIG_CMD_MII
57 #define CONFIG_CMD_PCI
59 #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
61 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */
62 #define CONFIG_SYS_LOWBOOT 1
64 /* RAMBOOT will be defined automatically in memory section */
66 #define CONFIG_JFFS2_CMDLINE
67 #define MTDIDS_DEFAULT "nor0=physmap-flash.0"
68 #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
69 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
71 /*-----------------------------------------------------------------------------
73 -----------------------------------------------------------------------------*/
74 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
75 #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
76 /* even with bootdelay=0 */
77 #undef CONFIG_BOOTARGS
79 #define CONFIG_PREBOOT "echo;" \
80 "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
81 "mount root filesystem over NFS;" \
84 #define CONFIG_EXTRA_ENV_SETTINGS \
86 "uimage=uImage-pcm030\0" \
87 "oftree=oftree-pcm030.dtb\0" \
88 "jffs2=root-pcm030.jffs2\0" \
89 "uboot=u-boot-pcm030.bin\0" \
90 "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \
92 "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \
93 " rootfstype=jffs2\0" \
94 "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \
95 " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \
96 "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
97 "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
98 " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
99 "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \
101 " cp.b 0x400000 0xff040000 $(filesize)\0" \
102 "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
103 "cp.b 0x400000 0xff200000 $(filesize)\0" \
104 "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
105 " cp.b 0x400000 0xfff40000 $(filesize)\0" \
106 "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
107 " cp.b 0x400000 0xFFF00000 $(filesize)\0" \
111 #define CONFIG_BOOTCOMMAND "run bcmd_flash"
113 /*--------------------------------------------------------------------------
114 IPB Bus clocking configuration.
115 ---------------------------------------------------------------------------*/
116 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
118 /*-------------------------------------------------------------------------
120 * 0x40000000 - 0x4fffffff - PCI Memory
121 * 0x50000000 - 0x50ffffff - PCI IO Space
122 * -----------------------------------------------------------------------*/
124 #define CONFIG_PCI_PNP 1
125 #define CONFIG_PCI_SCAN_SHOW 1
126 #define CONFIG_PCI_MEM_BUS 0x40000000
127 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
128 #define CONFIG_PCI_MEM_SIZE 0x10000000
129 #define CONFIG_PCI_IO_BUS 0x50000000
130 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
131 #define CONFIG_PCI_IO_SIZE 0x01000000
132 #define CONFIG_SYS_XLB_PIPELINING 1
134 /*---------------------------------------------------------------------------
136 ---------------------------------------------------------------------------*/
137 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
138 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
139 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
140 #define CONFIG_SYS_I2C_SLAVE 0x7F
142 /*---------------------------------------------------------------------------
143 EEPROM CAT24WC32 configuration
144 ---------------------------------------------------------------------------*/
145 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
146 #define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
147 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
148 #define CONFIG_SYS_EEPROM_SIZE 2048
149 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
150 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
152 /*---------------------------------------------------------------------------
154 ---------------------------------------------------------------------------*/
156 #define CONFIG_RTC_PCF8563 1
157 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
159 /*---------------------------------------------------------------------------
161 ---------------------------------------------------------------------------*/
163 #define CONFIG_SYS_FLASH_BASE 0xff000000
164 #define CONFIG_SYS_FLASH_SIZE 0x01000000
165 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
167 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
168 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
169 #define CONFIG_SYS_FLASH_EMPTY_INFO
170 #define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
171 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
172 /* (= chip selects) */
173 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
176 * Use also hardware protection. This seems required, as the BDI uses
177 * hardware protection. Without this, U-Boot can't work with this sectors,
178 * as its protection is software only by default
180 #define CONFIG_SYS_FLASH_PROTECTION 1
182 /*---------------------------------------------------------------------------
184 ---------------------------------------------------------------------------*/
186 /* pcm030 ships with environment is EEPROM by default */
187 #define CONFIG_ENV_IS_IN_EEPROM 1
188 #define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
189 /*beginning of the EEPROM */
190 #define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
192 #define CONFIG_ENV_OVERWRITE 1
194 /*-----------------------------------------------------------------------------
196 -----------------------------------------------------------------------------*/
197 #define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
198 /* bootloader or debugger config */
199 #define CONFIG_SYS_SDRAM_BASE 0x00000000
200 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
201 /* Use SRAM until RAM will be available */
202 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
203 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */
205 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
206 GENERATED_GBL_DATA_SIZE)
207 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
209 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
210 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
211 # define CONFIG_SYS_RAMBOOT 1
214 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
215 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
216 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
218 /*-----------------------------------------------------------------------------
219 Ethernet configuration
220 -----------------------------------------------------------------------------*/
221 #define CONFIG_MPC5xxx_FEC 1
222 #define CONFIG_MPC5xxx_FEC_MII100
223 #define CONFIG_PHY_ADDR 0x01
225 /*---------------------------------------------------------------------------
227 ---------------------------------------------------------------------------*/
229 /* GPIO port configuration
234 * PSC1_0 -> AC97 SDATA out
235 * PSC1_1 -> AC97 SDTA in
236 * PSC1_2 -> AC97 SYNC out
237 * PSC1_3 -> AC97 bitclock out
238 * PSC1_4 -> AC97 reset out
241 * PSC2_0 -> CAN 1 Tx out
242 * PSC2_1 -> CAN 1 Rx in
243 * PSC2_2 -> CAN 2 Tx out
244 * PSC2_3 -> CAN 2 Rx in
245 * PSC2_4 -> GPIO (claimed for ATA reset, active low)
249 * PSC3_0 -> UART Tx out
250 * PSC3_1 -> UART Rx in
251 * PSC3_2 -> UART RTS (in/out FIXME)
252 * PSC3_3 -> UART CTS (in/out FIXME)
253 * PSC3_4 -> LocalPlus Bus CS6 \
254 * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
255 * PSC3_6 -> dedicated SPI MOSI out (master case)
256 * PSC3_7 -> dedicated SPI MISO in (master case)
257 * PSC3_8 -> dedicated SPI SS out (master case)
258 * PSC3_9 -> dedicated SPI CLK out (master case)
261 * USB_0 -> USB OE out
262 * USB_1 -> USB Tx- out
263 * USB_2 -> USB Tx+ out
264 * USB_3 -> USB RxD (in/out FIXME)
265 * USB_4 -> USB Rx+ in
266 * USB_5 -> USB Rx- in
267 * USB_6 -> USB PortPower out
268 * USB_7 -> USB speed out
269 * USB_8 -> USB suspend (in/out FIXME)
270 * USB_9 -> USB overcurrent in
273 * USB differential mode
289 * ETH_10 -> ETH Collision
295 * ETH_16 -> ETH Rxerr
299 * PSC6_0 -> UART RxD in
300 * PSC6_1 -> UART CTS (in/out FIXME)
301 * PSC6_2 -> UART TxD out
302 * PSC6_3 -> UART RTS (in/out FIXME)
305 * TMR_0 -> ATA_CS0 out
306 * TMR_1 -> ATA_CS1 out
313 * I2C_0 -> I2C 1 Clock out
314 * I2C_1 -> I2C 1 IO in/out
315 * I2C_2 -> I2C 2 Clock out
316 * I2C_3 -> I2C 2 IO in/out
319 * PSC3_5 is used as CS7
322 * PSC3_4 is used as CS6
325 * gpio_wkup_7 is GPIO
328 * gpio_wkup_6 is GPIO
331 #define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12
333 /*-----------------------------------------------------------------------------
334 Miscellaneous configurable options
335 -------------------------------------------------------------------------------*/
336 #define CONFIG_SYS_LONGHELP /* undef to save memory */
338 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
340 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
341 #if defined(CONFIG_CMD_KGDB)
342 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
345 #if defined(CONFIG_CMD_KGDB)
346 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
348 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
350 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
351 /* Print Buffer Size */
352 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
353 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
355 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
356 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
358 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
360 #define CONFIG_DISPLAY_BOARDINFO 1
362 /*-----------------------------------------------------------------------------
363 Various low-level settings
364 -----------------------------------------------------------------------------*/
365 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
366 #define CONFIG_SYS_HID0_FINAL HID0_ICE
368 /* no burst access on the LPB */
369 #define CONFIG_SYS_CS_BURST 0x00000000
370 /* one deadcycle for the 33MHz statemachine */
371 #define CONFIG_SYS_CS_DEADCYCLE 0x33333331
372 /* one additional waitstate for the 33MHz statemachine */
373 #define CONFIG_SYS_BOOTCS_CFG 0x0001dd00
374 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
375 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
377 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
379 /*-----------------------------------------------------------------------
381 *-----------------------------------------------------------------------
383 #define CONFIG_USB_CLOCK 0x0001BBBB
384 #define CONFIG_USB_CONFIG 0x00001000
386 /*---------------------------------------------------------------------------
387 IDE/ATA stuff Supports IDE harddisk
388 ----------------------------------------------------------------------------*/
390 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
391 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
392 #undef CONFIG_IDE_LED /* LED for ide not supported */
393 #define CONFIG_SYS_ATA_CS_ON_TIMER01
394 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
395 #define CONFIG_IDE_PREINIT
396 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
397 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
398 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
399 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
400 /* Offset for data I/O */
401 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
402 /* Offset for normal register accesses */
403 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
404 /* Offset for alternate registers */
405 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
406 /* Interval between registers */
407 #define CONFIG_SYS_ATA_STRIDE 4
408 #define CONFIG_ATAPI 1
410 /* we enable IDE and FAT support, so we also need partition support */
411 #define CONFIG_DOS_PARTITION 1
414 #define CONFIG_USB_OHCI
415 #define CONFIG_USB_STORAGE
417 /* pass open firmware flat tree */
418 #define OF_CPU "PowerPC,5200@0"
419 #define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
420 #define OF_SOC "soc5200@f0000000"
421 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400"
423 #endif /* __CONFIG_H */