2 * Copyright (C) Stefano Babic <sbabic@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __PCM058_CONFIG_H
9 #define __PCM058_CONFIG_H
11 #include <config_distro_defaults.h>
14 #define CONFIG_SPL_SPI_LOAD
15 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
19 #include "mx6_common.h"
22 #define CONFIG_IMX_THERMAL
25 #define CONFIG_MXC_UART
26 #define CONFIG_MXC_UART_BASE UART2_BASE
27 #define CONSOLE_DEV "ttymxc1"
29 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
32 #define CONFIG_DISPLAY_BOARDINFO_LATE
35 /* Size of malloc() pool */
36 #define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
39 #define CONFIG_FEC_MXC
41 #define IMX_FEC_BASE ENET_BASE_ADDR
42 #define CONFIG_FEC_XCV_TYPE RGMII
43 #define CONFIG_ETHPRIME "FEC"
44 #define CONFIG_FEC_MXC_PHYADDR 3
46 #define CONFIG_PHY_MICREL
47 #define CONFIG_PHY_MICREL_KSZ90X1
50 #define CONFIG_MXC_SPI
51 #define CONFIG_SF_DEFAULT_BUS 0
52 #define CONFIG_SF_DEFAULT_CS 0
53 #define CONFIG_SF_DEFAULT_SPEED 20000000
54 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
57 #define CONFIG_SYS_I2C
58 #define CONFIG_SYS_I2C_MXC
59 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 2 */
60 #define CONFIG_SYS_I2C_SPEED 100000
62 #ifndef CONFIG_SPL_BUILD
63 /* Enable NAND support */
64 #define CONFIG_NAND_MXS
65 #define CONFIG_SYS_MAX_NAND_DEVICE 1
66 #define CONFIG_SYS_NAND_BASE 0x40000000
67 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
68 #define CONFIG_SYS_NAND_ONFI_DETECTION
71 /* DMA stuff, needed for GPMI/MXS NAND support */
72 #define CONFIG_APBH_DMA
73 #define CONFIG_APBH_DMA_BURST
74 #define CONFIG_APBH_DMA_BURST8
76 /* Filesystem support */
77 #define CONFIG_MTD_PARTITIONS
78 #define CONFIG_MTD_DEVICE
79 #define MTDIDS_DEFAULT "nand0=nand"
80 #define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
82 /* Physical Memory Map */
83 #define CONFIG_NR_DRAM_BANKS 1
84 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
86 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
87 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
88 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
90 #define CONFIG_SYS_INIT_SP_OFFSET \
91 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
92 #define CONFIG_SYS_INIT_SP_ADDR \
93 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
96 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
97 #define CONFIG_SYS_FSL_USDHC_NUM 1
99 /* Environment organization */
100 #define CONFIG_ENV_SIZE (16 * 1024)
101 #define CONFIG_ENV_OFFSET (1024 * SZ_1K)
102 #define CONFIG_ENV_SECT_SIZE (64 * SZ_1K)
103 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
104 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
105 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
106 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
107 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
108 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
109 CONFIG_ENV_SECT_SIZE)
110 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
112 #ifdef CONFIG_ENV_IS_IN_NAND
113 #define CONFIG_ENV_OFFSET (0x1E0000)
114 #define CONFIG_ENV_SECT_SIZE (128 * SZ_1K)