2 * Copyright (C) Stefano Babic <sbabic@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __PCM058_CONFIG_H
9 #define __PCM058_CONFIG_H
11 #include <config_distro_defaults.h>
14 #define CONFIG_SPL_SPI_LOAD
15 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
19 #include "mx6_common.h"
22 #define CONFIG_IMX_THERMAL
25 #define CONFIG_MXC_UART
26 #define CONFIG_MXC_UART_BASE UART2_BASE
27 #define CONSOLE_DEV "ttymxc1"
29 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
32 #define CONFIG_DISPLAY_BOARDINFO_LATE
35 /* Size of malloc() pool */
36 #define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
39 #define CONFIG_FEC_MXC
41 #define IMX_FEC_BASE ENET_BASE_ADDR
42 #define CONFIG_FEC_XCV_TYPE RGMII
43 #define CONFIG_ETHPRIME "FEC"
44 #define CONFIG_FEC_MXC_PHYADDR 3
47 #define CONFIG_PHY_MICREL
48 #define CONFIG_PHY_KSZ9031
51 #define CONFIG_MXC_SPI
52 #define CONFIG_SF_DEFAULT_BUS 0
53 #define CONFIG_SF_DEFAULT_CS 0
54 #define CONFIG_SF_DEFAULT_SPEED 20000000
55 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
58 #define CONFIG_SYS_I2C
59 #define CONFIG_SYS_I2C_MXC
60 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 2 */
61 #define CONFIG_SYS_I2C_SPEED 100000
63 #ifndef CONFIG_SPL_BUILD
64 /* Enable NAND support */
65 #define CONFIG_NAND_MXS
66 #define CONFIG_SYS_MAX_NAND_DEVICE 1
67 #define CONFIG_SYS_NAND_BASE 0x40000000
68 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
69 #define CONFIG_SYS_NAND_ONFI_DETECTION
72 /* DMA stuff, needed for GPMI/MXS NAND support */
73 #define CONFIG_APBH_DMA
74 #define CONFIG_APBH_DMA_BURST
75 #define CONFIG_APBH_DMA_BURST8
77 /* Filesystem support */
78 #define CONFIG_MTD_PARTITIONS
79 #define CONFIG_MTD_DEVICE
80 #define MTDIDS_DEFAULT "nand0=nand"
81 #define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
83 /* Physical Memory Map */
84 #define CONFIG_NR_DRAM_BANKS 1
85 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
87 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
88 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
89 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
91 #define CONFIG_SYS_INIT_SP_OFFSET \
92 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
93 #define CONFIG_SYS_INIT_SP_ADDR \
94 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
97 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
98 #define CONFIG_SYS_FSL_USDHC_NUM 1
100 /* Environment organization */
101 #define CONFIG_ENV_SIZE (16 * 1024)
102 #define CONFIG_ENV_OFFSET (1024 * SZ_1K)
103 #define CONFIG_ENV_SECT_SIZE (64 * SZ_1K)
104 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
105 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
106 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
107 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
108 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
109 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
110 CONFIG_ENV_SECT_SIZE)
111 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
113 #ifdef CONFIG_ENV_IS_IN_NAND
114 #define CONFIG_ENV_OFFSET (0x1E0000)
115 #define CONFIG_ENV_SECT_SIZE (128 * SZ_1K)