2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
7 * Configuation settings for the RONETIX PM9261 board.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * SoC must be defined first, before hardware.h is included.
33 * In this case SoC is defined in boards.cfg.
36 #include <asm/hardware.h>
37 /* ARM asynchronous clock */
39 #define CONFIG_DISPLAY_BOARDINFO
41 #define MASTER_PLL_DIV 15
42 #define MASTER_PLL_MUL 162
43 #define MAIN_PLL_DIV 2
44 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
45 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
47 #define CONFIG_SYS_HZ 1000
49 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
50 #define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */
51 #define CONFIG_ARCH_CPU_INIT
52 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
53 #define CONFIG_SYS_TEXT_BASE 0
56 /* CKGR_MOR - enable main osc. */
57 #define CONFIG_SYS_MOR_VAL \
58 (AT91_PMC_MOR_MOSCEN | \
59 (255 << 8)) /* Main Oscillator Start-up Time */
60 #define CONFIG_SYS_PLLAR_VAL \
61 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
62 AT91_PMC_PLLXR_OUT(3) | \
63 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
65 /* PCK/2 = MCK Master Clock from PLLA */
66 #define CONFIG_SYS_MCKR1_VAL \
67 (AT91_PMC_MCKR_CSS_SLOW | \
68 AT91_PMC_MCKR_PRES_1 | \
69 AT91_PMC_MCKR_MDIV_2 | \
70 AT91_PMC_MCKR_PLLADIV_1)
72 /* PCK/2 = MCK Master Clock from PLLA */
73 #define CONFIG_SYS_MCKR2_VAL \
74 (AT91_PMC_MCKR_CSS_PLLA | \
75 AT91_PMC_MCKR_PRES_1 | \
76 AT91_PMC_MCKR_MDIV_2 | \
77 AT91_PMC_MCKR_PLLADIV_1)
79 /* define PDC[31:16] as DATA[31:16] */
80 #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
81 /* no pull-up for D[31:16] */
82 #define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
84 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
85 #define CONFIG_SYS_MATRIX_EBICSA_VAL \
86 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
89 /* SDRAMC_MR Mode register */
90 #define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
91 /* SDRAMC_TR - Refresh Timer register */
92 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
93 /* SDRAMC_CR - Configuration register*/
94 #define CONFIG_SYS_SDRC_CR_VAL \
99 AT91_SDRAMC_DBW_32 | \
100 (1 << 8) | /* Write Recovery Delay */ \
101 (7 << 12) | /* Row Cycle Delay */ \
102 (3 << 16) | /* Row Precharge Delay */ \
103 (2 << 20) | /* Row to Column Delay */ \
104 (5 << 24) | /* Active to Precharge Delay */ \
105 (1 << 28)) /* Exit Self Refresh to Active Delay */
107 /* Memory Device Register -> SDRAM */
108 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
109 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
110 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
111 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
112 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
113 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
114 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
115 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
116 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
117 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
118 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
119 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
120 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
121 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
122 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
123 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
124 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
125 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
127 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
128 #define CONFIG_SYS_SMC0_SETUP0_VAL \
129 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
130 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
131 #define CONFIG_SYS_SMC0_PULSE0_VAL \
132 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
133 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
134 #define CONFIG_SYS_SMC0_CYCLE0_VAL \
135 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
136 #define CONFIG_SYS_SMC0_MODE0_VAL \
137 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
138 AT91_SMC_MODE_DBW_16 | \
139 AT91_SMC_MODE_TDF | \
140 AT91_SMC_MODE_TDF_CYCLE(6))
142 /* user reset enable */
143 #define CONFIG_SYS_RSTC_RMR_VAL \
145 AT91_RSTC_CR_PROCRST | \
146 AT91_RSTC_MR_ERSTL(1) | \
147 AT91_RSTC_MR_ERSTL(2))
149 /* Disable Watchdog */
150 #define CONFIG_SYS_WDTC_WDMR_VAL \
151 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
152 AT91_WDT_MR_WDV(0xfff) | \
153 AT91_WDT_MR_WDDIS | \
154 AT91_WDT_MR_WDD(0xfff))
156 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
157 #define CONFIG_SETUP_MEMORY_TAGS 1
158 #define CONFIG_INITRD_TAG 1
160 #undef CONFIG_SKIP_LOWLEVEL_INIT
165 #define CONFIG_AT91_GPIO 1
166 #define CONFIG_ATMEL_USART 1
167 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
168 #define CONFIG_USART_ID ATMEL_ID_SYS
172 #define LCD_BPP LCD_COLOR8
173 #define CONFIG_LCD_LOGO 1
174 #undef LCD_TEST_PATTERN
175 #define CONFIG_LCD_INFO 1
176 #define CONFIG_LCD_INFO_BELOW_LOGO 1
177 #define CONFIG_SYS_WHITE_ON_BLACK 1
178 #define CONFIG_ATMEL_LCD 1
179 #define CONFIG_ATMEL_LCD_BGR555 1
180 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
183 #define CONFIG_AT91_LED
184 #define CONFIG_RED_LED AT91_PIO_PORTC, 12
185 #define CONFIG_GREEN_LED AT91_PIO_PORTC, 13
186 #define CONFIG_YELLOW_LED AT91_PIO_PORTC, 15
188 #define CONFIG_BOOTDELAY 3
193 #define CONFIG_BOOTP_BOOTFILESIZE 1
194 #define CONFIG_BOOTP_BOOTPATH 1
195 #define CONFIG_BOOTP_GATEWAY 1
196 #define CONFIG_BOOTP_HOSTNAME 1
199 * Command line configuration.
201 #include <config_cmd_default.h>
202 #undef CONFIG_CMD_BDI
203 #undef CONFIG_CMD_IMI
204 #undef CONFIG_CMD_FPGA
205 #undef CONFIG_CMD_LOADS
206 #undef CONFIG_CMD_IMLS
208 #define CONFIG_CMD_CACHE
209 #define CONFIG_CMD_PING 1
210 #define CONFIG_CMD_DHCP 1
211 #define CONFIG_CMD_NAND 1
212 #define CONFIG_CMD_USB 1
215 #define CONFIG_NR_DRAM_BANKS 1
216 #define PHYS_SDRAM 0x20000000
217 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
220 #define CONFIG_ATMEL_DATAFLASH_SPI
221 #define CONFIG_HAS_DATAFLASH
222 #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
223 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
224 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
225 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */
226 #define AT91_SPI_CLK 15000000
227 #define DATAFLASH_TCSS (0x1a << 16)
228 #define DATAFLASH_TCHS (0x1 << 24)
231 #define CONFIG_NAND_ATMEL
232 #define NAND_MAX_CHIPS 1
233 #define CONFIG_SYS_MAX_NAND_DEVICE 1
234 #define CONFIG_SYS_NAND_BASE 0x40000000
235 #define CONFIG_SYS_NAND_DBW_8 1
236 /* our ALE is AD22 */
237 #define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
238 /* our CLE is AD21 */
239 #define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
240 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
241 #define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 16
244 #define CONFIG_SYS_FLASH_CFI 1
245 #define CONFIG_FLASH_CFI_DRIVER 1
246 #define PHYS_FLASH_1 0x10000000
247 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
248 #define CONFIG_SYS_MAX_FLASH_SECT 256
249 #define CONFIG_SYS_MAX_FLASH_BANKS 1
252 #define CONFIG_DRIVER_DM9000 1
253 #define CONFIG_DM9000_BASE 0x30000000
254 #define DM9000_IO CONFIG_DM9000_BASE
255 #define DM9000_DATA (CONFIG_DM9000_BASE + 4)
256 #define CONFIG_DM9000_USE_16BIT 1
257 #define CONFIG_NET_RETRY_COUNT 20
258 #define CONFIG_RESET_PHY_R 1
259 #define CONFIG_NET_MULTI
262 #define CONFIG_USB_ATMEL
263 #define CONFIG_USB_OHCI_NEW 1
264 #define CONFIG_DOS_PARTITION 1
265 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
266 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
267 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
268 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
269 #define CONFIG_USB_STORAGE 1
271 #define CONFIG_SYS_LOAD_ADDR 0x22000000
273 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
274 #define CONFIG_SYS_MEMTEST_END 0x23e00000
276 #undef CONFIG_SYS_USE_DATAFLASH_CS0
277 #undef CONFIG_SYS_USE_NANDFLASH
278 #define CONFIG_SYS_USE_FLASH 1
280 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
282 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
283 #define CONFIG_ENV_IS_IN_DATAFLASH 1
284 #define CONFIG_SYS_MONITOR_BASE \
285 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
286 #define CONFIG_ENV_OFFSET 0x4200
287 #define CONFIG_ENV_ADDR \
288 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
289 #define CONFIG_ENV_SIZE 0x4200
290 #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
291 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
292 "root=/dev/mtdblock0 " \
293 "mtdparts=atmel_nand:-(root) " \
294 "rw rootfstype=jffs2"
296 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
298 /* bootstrap + u-boot + env + linux in nandflash */
299 #define CONFIG_ENV_IS_IN_NAND 1
300 #define CONFIG_ENV_OFFSET 0x60000
301 #define CONFIG_ENV_OFFSET_REDUND 0x80000
302 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
303 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
304 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
305 "root=/dev/mtdblock5 " \
306 "mtdparts=atmel_nand:128k(bootstrap)ro," \
307 "256k(uboot)ro,128k(env1)ro," \
308 "128k(env2)ro,2M(linux),-(root) " \
309 "rw rootfstype=jffs2"
311 #elif defined (CONFIG_SYS_USE_FLASH)
313 #define CONFIG_ENV_IS_IN_FLASH 1
314 #define CONFIG_ENV_OFFSET 0x40000
315 #define CONFIG_ENV_SECT_SIZE 0x10000
316 #define CONFIG_ENV_SIZE 0x10000
317 #define CONFIG_ENV_OVERWRITE 1
319 /* JFFS Partition offset set */
320 #define CONFIG_SYS_JFFS2_FIRST_BANK 0
321 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
323 /* 512k reserved for u-boot */
324 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
326 #define CONFIG_BOOTCOMMAND "run flashboot"
328 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
329 #define MTDPARTS_DEFAULT \
330 "mtdparts=physmap-flash.0:" \
332 "64k(u-boot-env)ro," \
337 #define CONFIG_CON_ROT "fbcon=rotate:3 "
338 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT
340 #define CONFIG_EXTRA_ENV_SETTINGS \
341 "mtdids=" MTDIDS_DEFAULT "\0" \
342 "mtdparts=" MTDPARTS_DEFAULT "\0" \
343 "partition=nand0,0\0" \
344 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
345 "nfsargs=setenv bootargs root=/dev/nfs rw " \
347 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
348 "addip=setenv bootargs $(bootargs) " \
349 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
350 ":$(hostname):eth0:off\0" \
351 "ramboot=tftpboot 0x22000000 vmImage;" \
352 "run ramargs;run addip;bootm 22000000\0" \
353 "nfsboot=tftpboot 0x22000000 vmImage;" \
354 "run nfsargs;run addip;bootm 22000000\0" \
355 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
358 #error "Undefined memory device"
361 #define CONFIG_BAUDRATE 115200
362 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
364 #define CONFIG_SYS_PROMPT "pm9261> "
365 #define CONFIG_SYS_CBSIZE 256
366 #define CONFIG_SYS_MAXARGS 16
367 #define CONFIG_SYS_PBSIZE \
368 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
369 #define CONFIG_SYS_LONGHELP 1
370 #define CONFIG_CMDLINE_EDITING 1
373 * Size of malloc() pool
375 #define CONFIG_SYS_MALLOC_LEN \
376 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
378 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
379 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
380 GENERATED_GBL_DATA_SIZE)
382 #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
384 #ifdef CONFIG_USE_IRQ
385 #error CONFIG_USE_IRQ not supported