git.sur5r.net Git - u-boot/blob - include/configs/pm9261.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  * Ilko Iliev <www.ronetix.at>
   6  *
   7  * Configuation settings for the RONETIX PM9261 board.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * SoC must be defined first, before hardware.h is included.
  17  * In this case SoC is defined in boards.cfg.
  18  */
  19
  20 #include <asm/hardware.h>
  21 /* ARM asynchronous clock */
  22
  23 #define CONFIG_DISPLAY_BOARDINFO
  24
  25 #define MASTER_PLL_DIV          15
  26 #define MASTER_PLL_MUL          162
  27 #define MAIN_PLL_DIV            2
  28 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  29 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000
  30
  31 #define CONFIG_SYS_HZ           1000
  32
  33 #define CONFIG_SYS_AT91_CPU_NAME        "AT91SAM9261"
  34 #define CONFIG_PM9261           1       /* on a Ronetix PM9261 Board    */
  35 #define CONFIG_ARCH_CPU_INIT
  36 #define CONFIG_SYS_TEXT_BASE    0
  37
  38 #define MACH_TYPE_PM9261        1187
  39 #define CONFIG_MACH_TYPE        MACH_TYPE_PM9261
  40
  41 /* clocks */
  42 /* CKGR_MOR - enable main osc. */
  43 #define CONFIG_SYS_MOR_VAL                                              \
  44                 (AT91_PMC_MOR_MOSCEN |                                  \
  45                  (255 << 8))            /* Main Oscillator Start-up Time */
  46 #define CONFIG_SYS_PLLAR_VAL                                            \
  47                 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
  48                  AT91_PMC_PLLXR_OUT(3) |                                                \
  49                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  50
  51 /* PCK/2 = MCK Master Clock from PLLA */
  52 #define CONFIG_SYS_MCKR1_VAL            \
  53                 (AT91_PMC_MCKR_CSS_SLOW |       \
  54                  AT91_PMC_MCKR_PRES_1 | \
  55                  AT91_PMC_MCKR_MDIV_2 | \
  56                  AT91_PMC_MCKR_PLLADIV_1)
  57
  58 /* PCK/2 = MCK Master Clock from PLLA */
  59 #define CONFIG_SYS_MCKR2_VAL            \
  60                 (AT91_PMC_MCKR_CSS_PLLA |       \
  61                  AT91_PMC_MCKR_PRES_1 | \
  62                  AT91_PMC_MCKR_MDIV_2 | \
  63                  AT91_PMC_MCKR_PLLADIV_1)
  64
  65 /* define PDC[31:16] as DATA[31:16] */
  66 #define CONFIG_SYS_PIOC_PDR_VAL1        0xFFFF0000
  67 /* no pull-up for D[31:16] */
  68 #define CONFIG_SYS_PIOC_PPUDR_VAL       0xFFFF0000
  69
  70 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
  71 #define CONFIG_SYS_MATRIX_EBICSA_VAL            \
  72         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
  73
  74 /* SDRAM */
  75 /* SDRAMC_MR Mode register */
  76 #define CONFIG_SYS_SDRC_MR_VAL1         AT91_SDRAMC_MODE_NORMAL
  77 /* SDRAMC_TR - Refresh Timer register */
  78 #define CONFIG_SYS_SDRC_TR_VAL1         0x13C
  79 /* SDRAMC_CR - Configuration register*/
  80 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
  81                 (AT91_SDRAMC_NC_9 |                                             \
  82                  AT91_SDRAMC_NR_13 |                                            \
  83                  AT91_SDRAMC_NB_4 |                                             \
  84                  AT91_SDRAMC_CAS_3 |                                            \
  85                  AT91_SDRAMC_DBW_32 |                                           \
  86                  (1 <<  8) |            /* Write Recovery Delay */              \
  87                  (7 << 12) |            /* Row Cycle Delay */                   \
  88                  (3 << 16) |            /* Row Precharge Delay */               \
  89                  (2 << 20) |            /* Row to Column Delay */               \
  90                  (5 << 24) |            /* Active to Precharge Delay */         \
  91                  (1 << 28))             /* Exit Self Refresh to Active Delay */
  92
  93 /* Memory Device Register -> SDRAM */
  94 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
  95 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
  96 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
  97 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
  98 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
  99 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
 100 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
 101 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
 102 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
 103 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
 104 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
 105 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
 106 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
 107 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
 108 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
 109 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
 110 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
 111 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
 112
 113 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
 114 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
 115                 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
 116                  AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
 117 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
 118                 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
 119                  AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
 120 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
 121                 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
 122 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
 123                 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
 124                  AT91_SMC_MODE_DBW_16 |                         \
 125                  AT91_SMC_MODE_TDF |                            \
 126                  AT91_SMC_MODE_TDF_CYCLE(6))
 127
 128 /* user reset enable */
 129 #define CONFIG_SYS_RSTC_RMR_VAL                 \
 130                 (AT91_RSTC_KEY |                \
 131                 AT91_RSTC_CR_PROCRST |          \
 132                 AT91_RSTC_MR_ERSTL(1) | \
 133                 AT91_RSTC_MR_ERSTL(2))
 134
 135 /* Disable Watchdog */
 136 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
 137                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
 138                  AT91_WDT_MR_WDV(0xfff) |                                       \
 139                  AT91_WDT_MR_WDDIS |                            \
 140                  AT91_WDT_MR_WDD(0xfff))
 141
 142 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
 143 #define CONFIG_SETUP_MEMORY_TAGS 1
 144 #define CONFIG_INITRD_TAG       1
 145
 146 #undef CONFIG_SKIP_LOWLEVEL_INIT
 147 #define CONFIG_BOARD_EARLY_INIT_F
 148
 149 /*
 150  * Hardware drivers
 151  */
 152 #define CONFIG_AT91_GPIO        1
 153 #define CONFIG_ATMEL_USART      1
 154 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
 155 #define CONFIG_USART_ID                 ATMEL_ID_SYS
 156
 157 /* LCD */
 158 #define CONFIG_LCD                      1
 159 #define LCD_BPP                         LCD_COLOR8
 160 #define CONFIG_LCD_LOGO                 1
 161 #undef LCD_TEST_PATTERN
 162 #define CONFIG_LCD_INFO                 1
 163 #define CONFIG_LCD_INFO_BELOW_LOGO      1
 164 #define CONFIG_SYS_WHITE_ON_BLACK       1
 165 #define CONFIG_ATMEL_LCD                1
 166 #define CONFIG_ATMEL_LCD_BGR555         1
 167 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
 168
 169 /* LED */
 170 #define CONFIG_AT91_LED
 171 #define CONFIG_RED_LED          AT91_PIO_PORTC, 12
 172 #define CONFIG_GREEN_LED        AT91_PIO_PORTC, 13
 173 #define CONFIG_YELLOW_LED       AT91_PIO_PORTC, 15
 174
 175 #define CONFIG_BOOTDELAY        3
 176
 177 /*
 178  * BOOTP options
 179  */
 180 #define CONFIG_BOOTP_BOOTFILESIZE       1
 181 #define CONFIG_BOOTP_BOOTPATH           1
 182 #define CONFIG_BOOTP_GATEWAY            1
 183 #define CONFIG_BOOTP_HOSTNAME           1
 184
 185 /*
 186  * Command line configuration.
 187  */
 188 #include <config_cmd_default.h>
 189 #undef CONFIG_CMD_BDI
 190 #undef CONFIG_CMD_IMI
 191 #undef CONFIG_CMD_FPGA
 192 #undef CONFIG_CMD_LOADS
 193 #undef CONFIG_CMD_IMLS
 194
 195 #define CONFIG_CMD_CACHE
 196 #define CONFIG_CMD_PING         1
 197 #define CONFIG_CMD_DHCP         1
 198 #define CONFIG_CMD_NAND         1
 199 #define CONFIG_CMD_USB          1
 200
 201 /* SDRAM */
 202 #define CONFIG_NR_DRAM_BANKS                    1
 203 #define PHYS_SDRAM                              0x20000000
 204 #define PHYS_SDRAM_SIZE                         0x04000000      /* 64 megs */
 205
 206 /* DataFlash */
 207 #define CONFIG_ATMEL_DATAFLASH_SPI
 208 #define CONFIG_HAS_DATAFLASH
 209 #define CONFIG_SYS_SPI_WRITE_TOUT               (5 * CONFIG_SYS_HZ)
 210 #define CONFIG_SYS_MAX_DATAFLASH_BANKS          1
 211 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000      /* CS0 */
 212 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3     0xD0000000      /* CS3 */
 213 #define AT91_SPI_CLK                            15000000
 214 #define DATAFLASH_TCSS                          (0x1a << 16)
 215 #define DATAFLASH_TCHS                          (0x1 << 24)
 216
 217 /* NAND flash */
 218 #define CONFIG_NAND_ATMEL
 219 #define CONFIG_SYS_MAX_NAND_DEVICE              1
 220 #define CONFIG_SYS_NAND_BASE                    0x40000000
 221 #define CONFIG_SYS_NAND_DBW_8                   1
 222 /* our ALE is AD22 */
 223 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 22)
 224 /* our CLE is AD21 */
 225 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 21)
 226 #define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIO_PORTC, 14
 227 #define CONFIG_SYS_NAND_READY_PIN               AT91_PIO_PORTA, 16
 228
 229 /* NOR flash */
 230 #define CONFIG_SYS_FLASH_CFI                    1
 231 #define CONFIG_FLASH_CFI_DRIVER                 1
 232 #define PHYS_FLASH_1                            0x10000000
 233 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
 234 #define CONFIG_SYS_MAX_FLASH_SECT               256
 235 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 236
 237 /* Ethernet */
 238 #define CONFIG_DRIVER_DM9000                    1
 239 #define CONFIG_DM9000_BASE                      0x30000000
 240 #define DM9000_IO                               CONFIG_DM9000_BASE
 241 #define DM9000_DATA                             (CONFIG_DM9000_BASE + 4)
 242 #define CONFIG_DM9000_USE_16BIT                 1
 243 #define CONFIG_NET_RETRY_COUNT                  20
 244 #define CONFIG_RESET_PHY_R                      1
 245
 246 /* USB */
 247 #define CONFIG_USB_ATMEL
 248 #define CONFIG_USB_OHCI_NEW                     1
 249 #define CONFIG_DOS_PARTITION                    1
 250 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
 251 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00500000
 252 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9261"
 253 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 254 #define CONFIG_USB_STORAGE                      1
 255
 256 #define CONFIG_SYS_LOAD_ADDR                    0x22000000
 257
 258 #define CONFIG_SYS_MEMTEST_START                PHYS_SDRAM
 259 #define CONFIG_SYS_MEMTEST_END                  0x23e00000
 260
 261 #undef CONFIG_SYS_USE_DATAFLASH_CS0
 262 #undef CONFIG_SYS_USE_NANDFLASH
 263 #define CONFIG_SYS_USE_FLASH    1
 264
 265 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
 266
 267 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 268 #define CONFIG_ENV_IS_IN_DATAFLASH      1
 269 #define CONFIG_SYS_MONITOR_BASE         \
 270                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
 271 #define CONFIG_ENV_OFFSET       0x4200
 272 #define CONFIG_ENV_ADDR         \
 273                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 274 #define CONFIG_ENV_SIZE         0x4200
 275 #define CONFIG_BOOTCOMMAND      "cp.b 0xC0042000 0x22000000 0x210000; bootm"
 276 #define CONFIG_BOOTARGS         "console=ttyS0,115200 "                 \
 277                                 "root=/dev/mtdblock0 "                  \
 278                                 "mtdparts=atmel_nand:-(root) "          \
 279                                 "rw rootfstype=jffs2"
 280
 281 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
 282
 283 /* bootstrap + u-boot + env + linux in nandflash */
 284 #define CONFIG_ENV_IS_IN_NAND           1
 285 #define CONFIG_ENV_OFFSET               0x60000
 286 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 287 #define CONFIG_ENV_SIZE                 0x20000         /* 1 sector = 128 kB */
 288 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0xA0000 0x200000; bootm"
 289 #define CONFIG_BOOTARGS         "console=ttyS0,115200 "                 \
 290                                 "root=/dev/mtdblock5 "                  \
 291                                 "mtdparts=atmel_nand:128k(bootstrap)ro,"        \
 292                                 "256k(uboot)ro,128k(env1)ro,"           \
 293                                 "128k(env2)ro,2M(linux),-(root) "       \
 294                                 "rw rootfstype=jffs2"
 295
 296 #elif defined (CONFIG_SYS_USE_FLASH)
 297
 298 #define CONFIG_ENV_IS_IN_FLASH  1
 299 #define CONFIG_ENV_OFFSET       0x40000
 300 #define CONFIG_ENV_SECT_SIZE    0x10000
 301 #define CONFIG_ENV_SIZE         0x10000
 302 #define CONFIG_ENV_OVERWRITE    1
 303
 304 /* JFFS Partition offset set */
 305 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 306 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 307
 308 /* 512k reserved for u-boot */
 309 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   11
 310
 311 #define CONFIG_BOOTCOMMAND      "run flashboot"
 312
 313 #define MTDIDS_DEFAULT          "nor0=physmap-flash.0,nand0=nand"
 314 #define MTDPARTS_DEFAULT                \
 315         "mtdparts=physmap-flash.0:"     \
 316                 "256k(u-boot)ro,"       \
 317                 "64k(u-boot-env)ro,"    \
 318                 "1408k(kernel),"        \
 319                 "-(rootfs);"            \
 320         "nand:-(nand)"
 321
 322 #define CONFIG_CON_ROT "fbcon=rotate:3 "
 323 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT
 324
 325 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 326         "mtdids=" MTDIDS_DEFAULT "\0"                           \
 327         "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
 328         "partition=nand0,0\0"                                   \
 329         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
 330         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
 331                 CONFIG_CON_ROT                                  \
 332                 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
 333         "addip=setenv bootargs $(bootargs) "                    \
 334                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
 335                 ":$(hostname):eth0:off\0"                       \
 336         "ramboot=tftpboot 0x22000000 vmImage;"                  \
 337                 "run ramargs;run addip;bootm 22000000\0"        \
 338         "nfsboot=tftpboot 0x22000000 vmImage;"                  \
 339                 "run nfsargs;run addip;bootm 22000000\0"        \
 340         "flashboot=run ramargs;run addip;bootm 0x10050000\0"    \
 341         ""
 342 #else
 343 #error "Undefined memory device"
 344 #endif
 345
 346 #define CONFIG_BAUDRATE                 115200
 347
 348 #define CONFIG_SYS_PROMPT               "pm9261> "
 349 #define CONFIG_SYS_CBSIZE               256
 350 #define CONFIG_SYS_MAXARGS              16
 351 #define CONFIG_SYS_PBSIZE               \
 352                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 353 #define CONFIG_SYS_LONGHELP             1
 354 #define CONFIG_CMDLINE_EDITING  1
 355
 356 /*
 357  * Size of malloc() pool
 358  */
 359 #define CONFIG_SYS_MALLOC_LEN           \
 360                 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
 361
 362 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
 363 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 364                                 GENERATED_GBL_DATA_SIZE)
 365
 366 #endif