3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * Copied from lubbock.h
12 * BEC Systems <http://bec-systems.com>
13 * Cliff Brake <cliff.brake@gmail.com>
14 * Configuation settings for the Accelent/Vibren PXA255 IDP
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 #include <asm/arch/pxa-regs.h>
41 * If we are developing, we might want to start armboot from ram
42 * so we MUST NOT initialize critical regs like mem-timing ...
44 #define CONFIG_INIT_CRITICAL /* undef for developing */
47 * define the following to enable debug blinks. A debug blink function
48 * must be defined in memsetup.S
50 #undef DEBUG_BLINK_ENABLE
51 #undef DEBUG_BLINKC_ENABLE
54 * High Level Configuration Options
57 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
61 #define CONFIG_SHARP_LM8V31
65 #define BOARD_LATE_INIT 1
67 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
70 * Size of malloc() pool
72 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
73 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
76 * PXA250 IDP memory map information
79 #define IDP_CS5_ETH_OFFSET 0x03400000
85 #define CONFIG_DRIVER_SMC91111
86 #define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
87 #define CONFIG_SMC_USE_32_BIT 1
88 /* #define CONFIG_SMC_USE_IOFUNCS */
90 /* the following has to be set high -- suspect something is wrong with
91 * with the tftp timeout routines. FIXME!!!
93 #define CONFIG_NET_RETRY_COUNT 100
96 * select serial console configuration
98 #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
100 /* allow to overwrite serial and ethaddr */
101 #define CONFIG_ENV_OVERWRITE
103 #define CONFIG_BAUDRATE 115200
107 * Command line configuration.
109 #include <config_cmd_default.h>
111 #define CONFIG_CMD_MMC
112 #define CONFIG_CMD_FAT
113 #define CONFIG_CMD_DHCP
116 #define CONFIG_BOOTDELAY 3
117 #define CONFIG_BOOTCOMMAND "bootm 40000"
118 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
119 #define CONFIG_CMDLINE_TAG
122 * Current memory map for Vibren supplied Linux images:
125 * 0 - 0x3ffff (size = 0x40000): bootloader
126 * 0x40000 - 0x13ffff (size = 0x100000): kernel
127 * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
130 * 0xa0008000 - kernel is loaded
131 * 0xa3000000 - Uboot runs (48MB into RAM)
135 #define CONFIG_EXTRA_ENV_SETTINGS \
137 "mw.b 0xa0000000 0xff 0x40000; " \
139 "fatload mmc 0 0xa0000000 u-boot.bin; " \
141 "protect off 0x0 0x3ffff; " \
142 "erase 0x0 0x3ffff; " \
143 "cp.b 0xa0000000 0x0 0x40000; " \
146 "prog_uzImage_mmc=" \
147 "mw.b 0xa0000000 0xff 0x100000; " \
149 "fatload mmc 0 0xa0000000 uzImage; " \
151 "protect off 0x40000 0xfffff; " \
152 "erase 0x40000 0xfffff; " \
153 "cp.b 0xa0000000 0x40000 0x100000; " \
156 "mw.b 0xa0000000 0xff 0x1e00000; " \
158 "fatload mmc 0 0xa0000000 root.jffs; " \
160 "protect off 0x140000 0x1f3ffff; " \
161 "erase 0x140000 0x1f3ffff; " \
162 "cp.b 0xa0000000 0x140000 0x1e00000; " \
166 "fatload mmc 0 0xa1000000 uzImage && " \
168 "bootm 0xa1000000; " \
171 "mw.b 0xa0000000 0xff 0x100000; " \
172 "if bootp 0xa0000000 u-boot.bin; " \
174 "protect off 0x0 0x3ffff; " \
175 "erase 0x0 0x3ffff; " \
176 "cp.b 0xa0000000 0x0 0x40000; " \
179 "prog_uzImage_net=" \
180 "mw.b 0xa0000000 0xff 0x100000; " \
181 "if bootp 0xa0000000 uzImage; " \
183 "protect off 0x40000 0xfffff; " \
184 "erase 0x40000 0xfffff; " \
185 "cp.b 0xa0000000 0x40000 0x100000; " \
188 "mw.b 0xa0000000 0xff 0x1e00000; " \
189 "if bootp 0xa0000000 root.jffs; " \
191 "protect off 0x140000 0x1f3ffff; " \
192 "erase 0x140000 0x1f3ffff; " \
193 "cp.b 0xa0000000 0x140000 0x1e00000; " \
201 #if defined(CONFIG_CMD_KGDB)
202 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
203 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
207 * Miscellaneous configurable options
209 #define CFG_HUSH_PARSER 1
210 #define CFG_PROMPT_HUSH_PS2 "> "
212 #define CFG_LONGHELP /* undef to save memory */
213 #ifdef CFG_HUSH_PARSER
214 #define CFG_PROMPT "$ " /* Monitor Command Prompt */
216 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
218 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
219 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
220 #define CFG_MAXARGS 16 /* max number of command args */
221 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
222 #define CFG_DEVICE_NULLDEV 1
224 #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
225 #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
227 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
229 #define CFG_LOAD_ADDR 0xa0800000 /* default load address */
231 #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
232 #define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
234 #define RTC 1 /* enable 32KHz osc */
236 /* valid baudrates */
237 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
239 #define CFG_MMC_BASE 0xF0000000
244 * The stack sizes are set up in start.S using the settings below
246 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
247 #ifdef CONFIG_USE_IRQ
248 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
249 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
253 * Physical Memory Map
255 #define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */
256 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
257 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
258 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
259 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
260 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
261 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
262 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
263 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
265 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
266 #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
267 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
268 #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
269 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
271 #define CFG_DRAM_BASE 0xa0000000
272 #define CFG_DRAM_SIZE 0x04000000
274 #define CFG_FLASH_BASE PHYS_FLASH_1
280 #define CFG_GAFR0_L_VAL 0x80001005
281 #define CFG_GAFR0_U_VAL 0xa5128012
282 #define CFG_GAFR1_L_VAL 0x699a9558
283 #define CFG_GAFR1_U_VAL 0xaaa5aa6a
284 #define CFG_GAFR2_L_VAL 0xaaaaaaaa
285 #define CFG_GAFR2_U_VAL 0x2
286 #define CFG_GPCR0_VAL 0x1800400
287 #define CFG_GPCR1_VAL 0x0
288 #define CFG_GPCR2_VAL 0x0
289 #define CFG_GPDR0_VAL 0xc1818440
290 #define CFG_GPDR1_VAL 0xfcffab82
291 #define CFG_GPDR2_VAL 0x1ffff
292 #define CFG_GPSR0_VAL 0x8000
293 #define CFG_GPSR1_VAL 0x3f0002
294 #define CFG_GPSR2_VAL 0x1c000
296 #define CFG_PSSR_VAL 0x20
301 #define CFG_MSC0_VAL 0x29DCA4D2
302 #define CFG_MSC1_VAL 0x43AC494C
303 #define CFG_MSC2_VAL 0x39D449D4
304 #define CFG_MDCNFG_VAL 0x090009C9
305 #define CFG_MDREFR_VAL 0x0085C017
306 #define CFG_MDMRS_VAL 0x00220022
309 * PCMCIA and CF Interfaces
311 #define CFG_MECR_VAL 0x00000003
312 #define CFG_MCMEM0_VAL 0x00014405
313 #define CFG_MCMEM1_VAL 0x00014405
314 #define CFG_MCATT0_VAL 0x00014405
315 #define CFG_MCATT1_VAL 0x00014405
316 #define CFG_MCIO0_VAL 0x00014405
317 #define CFG_MCIO1_VAL 0x00014405
320 * FLASH and environment organization
322 #define CFG_FLASH_CFI
323 #define CFG_FLASH_CFI_DRIVER 1
325 #define CFG_MONITOR_BASE 0
326 #define CFG_MONITOR_LEN 0x40000
328 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
329 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
331 #define CFG_FLASH_USE_BUFFER_WRITE 1
333 /* timeout values are in ticks */
334 #define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
335 #define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
337 /* put cfg at end of flash for now */
338 #define CFG_ENV_IS_IN_FLASH 1
339 /* Addr of Environment Sector */
340 #define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
341 #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
342 #define CFG_ENV_SECT_SIZE 0x40000
344 #endif /* __CONFIG_H */