2 * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
4 * Configuration settings for the Dave/DENX QongEVB-LITE board.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
27 /* High Level Configuration Options */
28 #define CONFIG_ARM1136 /* This is an arm1136 CPU core */
29 #define CONFIG_MX31 /* in a mx31 */
31 #define CONFIG_MX31_HCLK_FREQ 26000000 /* 26MHz */
32 #define CONFIG_MX31_CLK32 32768
34 #define CONFIG_DISPLAY_CPUINFO
35 #define CONFIG_DISPLAY_BOARDINFO
37 #define CONFIG_SYS_TEXT_BASE 0xa0000000
39 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
40 #define CONFIG_SETUP_MEMORY_TAGS
41 #define CONFIG_INITRD_TAG
44 * Size of malloc() pool
46 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
52 #define CONFIG_MXC_UART 1
53 #define CONFIG_SYS_MX31_UART1 1
55 #define CONFIG_MXC_GPIO
56 #define CONFIG_HW_WATCHDOG
58 #define CONFIG_MXC_SPI
59 #define CONFIG_DEFAULT_SPI_BUS 1
60 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
61 #define CONFIG_RTC_MC13783
64 #define CONFIG_PMIC_SPI
65 #define CONFIG_PMIC_FSL
66 #define CONFIG_FSL_PMIC_BUS 1
67 #define CONFIG_FSL_PMIC_CS 0
68 #define CONFIG_FSL_PMIC_CLK 100000
69 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
70 #define CONFIG_FSL_PMIC_BITLEN 32
74 #define CONFIG_QONG_FPGA
75 #define CONFIG_FPGA_BASE (CS1_BASE)
76 #define CONFIG_FPGA_LATTICE
77 #define CONFIG_FPGA_COUNT 1
79 #ifdef CONFIG_QONG_FPGA
82 #define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
84 /* Framebuffer and LCD */
86 #define CONFIG_CFB_CONSOLE
87 #define CONFIG_VIDEO_MX3
88 #define CONFIG_VIDEO_LOGO
89 #define CONFIG_VIDEO_SW_CURSOR
90 #define CONFIG_VGA_AS_SINGLE_DEVICE
91 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
92 #define CONFIG_SPLASH_SCREEN
93 #define CONFIG_CMD_BMP
94 #define CONFIG_BMP_16BPP
97 #define CONFIG_CMD_USB
99 #define CONFIG_USB_EHCI /* Enable EHCI USB support */
100 #define CONFIG_USB_EHCI_MXC
101 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
102 #define CONFIG_MXC_USB_PORT 2
103 #define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
104 #define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
105 #define CONFIG_EHCI_IS_TDI
106 #define CONFIG_USB_STORAGE
107 #define CONFIG_DOS_PARTITION
108 #define CONFIG_SUPPORT_VFAT
109 #define CONFIG_CMD_EXT2
110 #define CONFIG_CMD_FAT
111 #endif /* CONFIG_CMD_USB */
114 * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
115 * initial TFTP transfer, should the user wish one, significantly.
117 #define CONFIG_ARP_TIMEOUT 200UL
119 #endif /* CONFIG_QONG_FPGA */
121 #define CONFIG_CONS_INDEX 1
122 #define CONFIG_BAUDRATE 115200
123 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
125 /***********************************************************
127 ***********************************************************/
129 #include <config_cmd_default.h>
131 #define CONFIG_CMD_CACHE
132 #define CONFIG_CMD_DATE
133 #define CONFIG_CMD_DHCP
134 #define CONFIG_CMD_MII
135 #define CONFIG_CMD_NAND
136 #define CONFIG_CMD_NET
137 #define CONFIG_CMD_PING
138 #define CONFIG_CMD_SETEXPR
139 #define CONFIG_CMD_SPI
141 #define CONFIG_BOARD_LATE_INIT
143 #define CONFIG_BOOTDELAY 5
145 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
147 #define xstr(s) str(s)
150 #define CONFIG_EXTRA_ENV_SETTINGS \
152 "nfsargs=setenv bootargs root=/dev/nfs rw " \
153 "nfsroot=${serverip}:${rootpath}\0" \
154 "ramargs=setenv bootargs root=/dev/ram rw\0" \
155 "addip=setenv bootargs ${bootargs} " \
156 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
157 ":${hostname}:${netdev}:off panic=1\0" \
158 "addtty=setenv bootargs ${bootargs}" \
159 " console=ttymxc0,${baudrate}\0" \
160 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
161 "addmisc=setenv bootargs ${bootargs}\0" \
162 "uboot_addr=A0000000\0" \
163 "kernel_addr=A00C0000\0" \
164 "ramdisk_addr=A0300000\0" \
165 "u-boot=qong/u-boot.bin\0" \
166 "kernel_addr_r=80800000\0" \
168 "bootfile=qong/uImage\0" \
169 "rootpath=/opt/eldk-4.2-arm/armVFP\0" \
170 "flash_self=run ramargs addip addtty addmtd addmisc;" \
171 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
172 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
173 "bootm ${kernel_addr}\0" \
174 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
175 "run nfsargs addip addtty addmtd addmisc;" \
177 "bootcmd=run flash_self\0" \
178 "load=tftp ${loadaddr} ${u-boot}\0" \
179 "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
180 " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
181 " +${filesize};cp.b ${fileaddr} " \
182 xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
183 "upd=run load update\0" \
184 "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \
185 "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \
189 * Miscellaneous configurable options
191 #define CONFIG_SYS_LONGHELP /* undef to save memory */
192 #define CONFIG_SYS_PROMPT "=> "
193 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
194 /* Print Buffer Size */
195 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
196 sizeof(CONFIG_SYS_PROMPT) + 16)
197 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
198 /* Boot Argument Buffer Size */
199 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
201 /* memtest works on first 255MB of RAM */
202 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
203 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000)
205 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
207 #define CONFIG_SYS_HZ 1000
209 #define CONFIG_CMDLINE_EDITING
210 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
211 #ifdef CONFIG_SYS_HUSH_PARSER
212 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
215 #define CONFIG_MISC_INIT_R
216 /*-----------------------------------------------------------------------
219 * The stack sizes are set up in start.S using the settings below
221 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
223 /*-----------------------------------------------------------------------
224 * Physical Memory Map
226 #define CONFIG_NR_DRAM_BANKS 1
227 #define PHYS_SDRAM_1 CSD0_BASE
228 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
235 extern void qong_nand_plat_init(void *chip);
236 extern int qong_nand_rdy(void *chip);
238 #define CONFIG_NAND_PLAT
239 #define CONFIG_SYS_MAX_NAND_DEVICE 1
240 #define CONFIG_SYS_NAND_BASE CS3_BASE
241 #define NAND_PLAT_INIT() qong_nand_plat_init(nand)
243 #define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24))
244 #define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23))
245 #define QONG_NAND_WRITE(addr, cmd) \
247 __REG8(addr) = cmd; \
250 #define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
251 #define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
252 #define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip))
254 /*-----------------------------------------------------------------------
255 * FLASH and environment organization
257 #define CONFIG_SYS_FLASH_BASE CS0_BASE
258 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
259 /* max number of sectors on one chip */
260 #define CONFIG_SYS_MAX_FLASH_SECT 1024
261 /* Monitor at beginning of flash */
262 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
263 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
265 #define CONFIG_ENV_IS_IN_FLASH
266 #define CONFIG_ENV_SECT_SIZE 0x20000
267 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
268 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
270 /* Address and size of Redundant Environment Sector */
271 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
272 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
274 /*-----------------------------------------------------------------------
275 * CFI FLASH driver setup
277 /* Flash memory is CFI compliant */
278 #define CONFIG_SYS_FLASH_CFI
279 /* Use drivers/cfi_flash.c */
280 #define CONFIG_FLASH_CFI_DRIVER
281 /* Use buffered writes (~10x faster) */
282 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
283 /* Use hardware sector protection */
284 #define CONFIG_SYS_FLASH_PROTECTION
289 #define CONFIG_CMD_JFFS2
290 #define CONFIG_CMD_UBI
291 #define CONFIG_CMD_UBIFS
292 #define CONFIG_RBTREE
293 #define CONFIG_MTD_PARTITIONS
294 #define CONFIG_CMD_MTDPARTS
296 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
297 #define CONFIG_FLASH_CFI_MTD
298 #define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
300 #define MTDPARTS_DEFAULT \
301 "mtdparts=physmap-flash.0:" \
302 "512k(U-Boot),128k(env1),128k(env2)," \
303 "2304k(kernel),13m(ramdisk),-(user);" \
307 /* additions for new relocation code, must be added to all boards */
308 #define CONFIG_SYS_SDRAM_BASE 0x80000000
309 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
310 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
311 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
312 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
314 #define CONFIG_BOARD_EARLY_INIT_F
316 #endif /* __CONFIG_H */