2 * Configuration settings for the SAMA5D2 PTC Engineering board.
4 * Copyright (C) 2016 Atmel
5 * Wenyou Yang <wenyou.yang@atmel.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include "at91-sama5_common.h"
16 #define CONFIG_ATMEL_USART
17 #define CONFIG_USART_BASE 0xf801c000
18 #define CONFIG_USART_ID 24
20 #define CONFIG_SYS_SDRAM_BASE 0x20000000
21 #define CONFIG_SYS_SDRAM_SIZE 0x20000000
23 #define CONFIG_SYS_TIMER_COUNTER 0xf804803c
25 #ifdef CONFIG_SPL_BUILD
26 #define CONFIG_SYS_INIT_SP_ADDR 0x210000
28 #define CONFIG_SYS_INIT_SP_ADDR \
29 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
32 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
34 #undef CONFIG_AT91_GPIO
35 #define CONFIG_ATMEL_PIO4
38 #define CONFIG_NR_DRAM_BANKS 1
42 #define CONFIG_ATMEL_SPI
43 #define CONFIG_SPI_FLASH_ATMEL
44 #define CONFIG_SF_DEFAULT_BUS 0
45 #define CONFIG_SF_DEFAULT_CS 0
46 #define CONFIG_SF_DEFAULT_SPEED 30000000
50 #ifdef CONFIG_CMD_NAND
51 #define CONFIG_NAND_ATMEL
52 #define CONFIG_SYS_MAX_NAND_DEVICE 1
53 #define CONFIG_SYS_NAND_BASE 0x80000000
55 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
57 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
58 #define CONFIG_SYS_NAND_ONFI_DETECTION
59 /* PMECC & PMERRLOC */
60 #define CONFIG_ATMEL_NAND_HWECC
61 #define CONFIG_ATMEL_NAND_HW_PMECC
65 #define CONFIG_USB_ETHER
66 #define CONFIG_USB_ETH_RNDIS
67 #define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2_PTC"
69 /* Ethernet Hardware */
72 #define CONFIG_NET_RETRY_COUNT 20
73 #define CONFIG_MACB_SEARCH_PHY
75 #ifdef CONFIG_NAND_BOOT
76 #undef CONFIG_ENV_OFFSET
77 #undef CONFIG_ENV_OFFSET_REDUND
78 #undef CONFIG_BOOTCOMMAND
79 /* u-boot env in nand flash */
80 #define CONFIG_ENV_OFFSET 0x200000
81 #define CONFIG_ENV_OFFSET_REDUND 0x400000
82 #define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xb80000 0x80000;" \
83 "nand read 0x22000000 0x600000 0x600000;" \
84 "bootz 0x22000000 - 0x21000000"
88 #define CONFIG_SPL_FRAMEWORK
89 #define CONFIG_SPL_TEXT_BASE 0x200000
90 #define CONFIG_SPL_MAX_SIZE 0x10000
91 #define CONFIG_SPL_BSS_START_ADDR 0x20000000
92 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
93 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000
94 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
96 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
98 #ifdef CONFIG_SPI_BOOT
99 #define CONFIG_SPL_SPI_LOAD
100 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
102 #elif CONFIG_NAND_BOOT
103 #define CONFIG_SPL_NAND_DRIVERS
104 #define CONFIG_SPL_NAND_BASE
106 #define CONFIG_PMECC_CAP 8
107 #define CONFIG_PMECC_SECTOR_SIZE 512
108 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
109 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
110 #define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
111 #define CONFIG_SYS_NAND_PAGE_COUNT 64
112 #define CONFIG_SYS_NAND_OOBSIZE 224
113 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
114 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
115 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER