2 * Copyright 2007,2009 Wind River Systems <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 * Copyright 2004, 2007 Freescale Semiconductor.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * sbc8548 board configuration file
27 * Please refer to doc/README.sbc8548 for more info.
33 * Top level Makefile configuration choices
36 #define CONFIG_PCI_INDIRECT_BRIDGE
41 #define CONFIG_SYS_CLK_DIV 1
45 #define CONFIG_SYS_CLK_DIV 2
53 * High Level Configuration Options
55 #define CONFIG_BOOKE 1 /* BOOKE */
56 #define CONFIG_E500 1 /* BOOKE e500 family */
57 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
58 #define CONFIG_MPC8548 1 /* MPC8548 specific */
59 #define CONFIG_SBC8548 1 /* SBC8548 board specific */
62 * If you want to boot from the SODIMM flash, instead of the soldered
63 * on flash, set this, and change JP12, SW2:8 accordingly.
65 #undef CONFIG_SYS_ALT_BOOT
67 #ifndef CONFIG_SYS_TEXT_BASE
68 #ifdef CONFIG_SYS_ALT_BOOT
69 #define CONFIG_SYS_TEXT_BASE 0xfff00000
71 #define CONFIG_SYS_TEXT_BASE 0xfffa0000
78 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
79 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
82 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
85 #define CONFIG_TSEC_ENET /* tsec ethernet support */
86 #define CONFIG_ENV_OVERWRITE
88 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
90 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
93 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
95 #ifndef CONFIG_SYS_CLK_DIV
96 #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
98 #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
101 * These can be toggled for performance analysis, otherwise use default.
103 #define CONFIG_L2_CACHE /* toggle L2 cache */
104 #define CONFIG_BTB /* toggle branch predition */
107 * Only possible on E500 Version 2 or newer cores.
109 #define CONFIG_ENABLE_36BIT_PHYS 1
111 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
113 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
114 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
115 #define CONFIG_SYS_MEMTEST_END 0x00400000
117 #define CONFIG_SYS_CCSRBAR 0xe0000000
118 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
121 #define CONFIG_FSL_DDR2
122 #undef CONFIG_FSL_DDR_INTERACTIVE
123 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
125 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
126 * to collide, meaning you couldn't reliably read either. So
127 * physically remove the LBC PC100 SDRAM module from the board
128 * before enabling the two SPD options below, or check that you
129 * have the hardware fix on your board via "i2c probe" and looking
130 * for a device at 0x53.
132 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
133 #undef CONFIG_DDR_SPD
135 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
136 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
138 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
139 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
140 #define CONFIG_VERY_BIG_RAM
142 #define CONFIG_NUM_DDR_CONTROLLERS 1
143 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
144 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
147 * The hardware fix for the I2C address collision puts the DDR
148 * SPD at 0x53, but if we are running on an older board w/o the
149 * fix, it will still be at 0x51. We check 0x53 1st.
151 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
152 #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */
155 * Make sure required options are set
157 #ifndef CONFIG_SPD_EEPROM
158 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
159 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
162 #undef CONFIG_CLOCKS_IN_MHZ
165 * FLASH on the Local Bus
166 * Two banks, one 8MB the other 64MB, using the CFI driver.
167 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
168 * CS0 the 8MB boot flash, and CS6 the 64MB flash.
171 * ec00_0000 efff_ffff 64MB SODIMM
172 * ff80_0000 ffff_ffff 8MB soldered flash
175 * ef80_0000 efff_ffff 8MB soldered flash
176 * fc00_0000 ffff_ffff 64MB SODIMM
179 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
180 * Port Size = 8 bits = BRx[19:20] = 01
181 * Use GPCM = BRx[24:26] = 000
182 * Valid = BRx[31] = 1
185 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
186 * Port Size = 32 bits = BRx[19:20] = 11
188 * 0 4 8 12 16 20 24 28
189 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M
190 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M
192 #define CONFIG_SYS_BR0_8M 0xff800801
193 #define CONFIG_SYS_BR0_64M 0xfc001801
197 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
198 * Port Size = 8 bits = BRx[19:20] = 01
199 * Use GPCM = BRx[24:26] = 000
200 * Valid = BRx[31] = 1
203 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
204 * Port Size = 32 bits = BRx[19:20] = 11
206 * 0 4 8 12 16 20 24 28
207 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M
208 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M
210 #define CONFIG_SYS_BR6_8M 0xef800801
211 #define CONFIG_SYS_BR6_64M 0xec001801
215 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
216 * XAM = OR0[17:18] = 11
218 * ACS = half cycle delay = OR0[21:22] = 11
219 * SCY = 6 = OR0[24:27] = 0110
220 * TRLX = use relaxed timing = OR0[29] = 1
221 * EAD = use external address latch delay = OR0[31] = 1
224 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
227 * 0 4 8 12 16 20 24 28
228 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M
229 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M
231 #define CONFIG_SYS_OR0_8M 0xff806e65
232 #define CONFIG_SYS_OR0_64M 0xfc006e65
236 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
237 * XAM = OR6[17:18] = 11
239 * ACS = half cycle delay = OR6[21:22] = 11
240 * SCY = 6 = OR6[24:27] = 0110
241 * TRLX = use relaxed timing = OR6[29] = 1
242 * EAD = use external address latch delay = OR6[31] = 1
245 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
247 * 0 4 8 12 16 20 24 28
248 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M
249 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M
251 #define CONFIG_SYS_OR6_8M 0xff806e65
252 #define CONFIG_SYS_OR6_64M 0xfc006e65
254 #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */
255 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
256 #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */
258 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M
259 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M
261 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M
262 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M
263 #else /* JP12 in alternate position */
264 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */
265 #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */
267 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M
268 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M
270 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M
271 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M
274 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK
275 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
276 CONFIG_SYS_ALT_FLASH}
277 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
278 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
279 #undef CONFIG_SYS_FLASH_CHECKSUM
280 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
281 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
283 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
285 #define CONFIG_FLASH_CFI_DRIVER
286 #define CONFIG_SYS_FLASH_CFI
287 #define CONFIG_SYS_FLASH_EMPTY_INFO
289 /* CS5 = Local bus peripherals controlled by the EPLD */
291 #define CONFIG_SYS_BR5_PRELIM 0xf8000801
292 #define CONFIG_SYS_OR5_PRELIM 0xff006e65
293 #define CONFIG_SYS_EPLD_BASE 0xf8000000
294 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000
295 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
296 #define CONFIG_SYS_BD_REV 0xf8300000
297 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000
300 * SDRAM on the Local Bus (CS3 and CS4)
301 * Note that most boards have a hardware errata where both the
302 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
303 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
304 * A hardware workaround is also available, see README.sbc8548 file.
306 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
307 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
310 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
311 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
314 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
315 * port-size = 32-bits = BR2[19:20] = 11
316 * no parity checking = BR2[21:22] = 00
317 * SDRAM for MSEL = BR2[24:26] = 011
320 * 0 4 8 12 16 20 24 28
321 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
325 #define CONFIG_SYS_BR3_PRELIM 0xf0001861
328 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
331 * 64MB mask for AM, OR3[0:7] = 1111 1100
332 * XAM, OR3[17:18] = 11
333 * 10 columns OR3[19-21] = 011
334 * 12 rows OR3[23-25] = 011
335 * EAD set for extra time OR[31] = 0
337 * 0 4 8 12 16 20 24 28
338 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
341 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
344 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
345 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
348 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
349 * port-size = 32-bits = BR2[19:20] = 11
350 * no parity checking = BR2[21:22] = 00
351 * SDRAM for MSEL = BR2[24:26] = 011
354 * 0 4 8 12 16 20 24 28
355 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
359 #define CONFIG_SYS_BR4_PRELIM 0xf4001861
362 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
365 * 64MB mask for AM, OR3[0:7] = 1111 1100
366 * XAM, OR3[17:18] = 11
367 * 10 columns OR3[19-21] = 011
368 * 12 rows OR3[23-25] = 011
369 * EAD set for extra time OR[31] = 0
371 * 0 4 8 12 16 20 24 28
372 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
375 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
377 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
378 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
379 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
380 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
383 * Common settings for all Local Bus SDRAM commands.
385 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
395 #define CONFIG_SYS_LBC_LSDMR_PCHALL \
396 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
397 #define CONFIG_SYS_LBC_LSDMR_ARFRSH \
398 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
399 #define CONFIG_SYS_LBC_LSDMR_MRW \
400 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
401 #define CONFIG_SYS_LBC_LSDMR_RFEN \
402 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
404 #define CONFIG_SYS_INIT_RAM_LOCK 1
405 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
406 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
408 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
410 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
411 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
414 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
415 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
416 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
417 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
418 * thing for MONITOR_LEN in both cases.
420 #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
421 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
424 #define CONFIG_CONS_INDEX 1
425 #define CONFIG_SYS_NS16550
426 #define CONFIG_SYS_NS16550_SERIAL
427 #define CONFIG_SYS_NS16550_REG_SIZE 1
428 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
430 #define CONFIG_SYS_BAUDRATE_TABLE \
431 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
433 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
434 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
436 /* Use the HUSH parser */
437 #define CONFIG_SYS_HUSH_PARSER
439 /* pass open firmware flat tree */
440 #define CONFIG_OF_LIBFDT 1
441 #define CONFIG_OF_BOARD_SETUP 1
442 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
447 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
448 #define CONFIG_HARD_I2C /* I2C with hardware support*/
449 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
450 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
451 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
452 #define CONFIG_SYS_I2C_SLAVE 0x7F
453 #define CONFIG_SYS_I2C_OFFSET 0x3000
457 * Memory space is mapped 1-1, but I/O space must start from 0.
459 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
460 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
462 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
463 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
464 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
465 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
466 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
467 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
468 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
469 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
472 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
473 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
474 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
475 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
476 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
477 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
478 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
479 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
486 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
487 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
490 #if defined(CONFIG_PCI)
492 #define CONFIG_PCI_PNP /* do pci plug-and-play */
494 #undef CONFIG_EEPRO100
497 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
499 #endif /* CONFIG_PCI */
502 #if defined(CONFIG_TSEC_ENET)
504 #define CONFIG_MII 1 /* MII PHY management */
505 #define CONFIG_TSEC1 1
506 #define CONFIG_TSEC1_NAME "eTSEC0"
507 #define CONFIG_TSEC2 1
508 #define CONFIG_TSEC2_NAME "eTSEC1"
509 #undef CONFIG_MPC85XX_FEC
511 #define TSEC1_PHY_ADDR 0x19
512 #define TSEC2_PHY_ADDR 0x1a
514 #define TSEC1_PHYIDX 0
515 #define TSEC2_PHYIDX 0
517 #define TSEC1_FLAGS TSEC_GIGABIT
518 #define TSEC2_FLAGS TSEC_GIGABIT
520 /* Options are: eTSEC[0-3] */
521 #define CONFIG_ETHPRIME "eTSEC0"
522 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
523 #endif /* CONFIG_TSEC_ENET */
528 #define CONFIG_ENV_IS_IN_FLASH 1
529 #define CONFIG_ENV_SIZE 0x2000
530 #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
531 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
532 #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */
533 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
534 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
535 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
537 #warning undefined environment size/location.
540 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
541 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
546 #define CONFIG_BOOTP_BOOTFILESIZE
547 #define CONFIG_BOOTP_BOOTPATH
548 #define CONFIG_BOOTP_GATEWAY
549 #define CONFIG_BOOTP_HOSTNAME
553 * Command line configuration.
555 #include <config_cmd_default.h>
557 #define CONFIG_CMD_PING
558 #define CONFIG_CMD_I2C
559 #define CONFIG_CMD_MII
560 #define CONFIG_CMD_ELF
561 #define CONFIG_CMD_REGINFO
563 #if defined(CONFIG_PCI)
564 #define CONFIG_CMD_PCI
568 #undef CONFIG_WATCHDOG /* watchdog disabled */
571 * Miscellaneous configurable options
573 #define CONFIG_CMDLINE_EDITING /* undef to save memory */
574 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
575 #define CONFIG_SYS_LONGHELP /* undef to save memory */
576 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
577 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
578 #if defined(CONFIG_CMD_KGDB)
579 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
581 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
583 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
584 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
585 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
586 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
589 * For booting Linux, the board info and command line data
590 * have to be in the first 8 MB of memory, since this is
591 * the maximum mapped by the Linux kernel during initialization.
593 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
595 #if defined(CONFIG_CMD_KGDB)
596 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
597 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
601 * Environment Configuration
604 /* The mac addresses for all ethernet interface */
605 #if defined(CONFIG_TSEC_ENET)
606 #define CONFIG_HAS_ETH0
607 #define CONFIG_ETHADDR 02:E0:0C:00:00:FD
608 #define CONFIG_HAS_ETH1
609 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
612 #define CONFIG_IPADDR 192.168.0.55
614 #define CONFIG_HOSTNAME sbc8548
615 #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx"
616 #define CONFIG_BOOTFILE "/uImage"
617 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
619 #define CONFIG_SERVERIP 192.168.0.2
620 #define CONFIG_GATEWAYIP 192.168.0.1
621 #define CONFIG_NETMASK 255.255.255.0
623 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
625 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
626 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
628 #define CONFIG_BAUDRATE 115200
630 #define CONFIG_EXTRA_ENV_SETTINGS \
632 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
633 "tftpflash=tftpboot $loadaddr $uboot; " \
634 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
635 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
636 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
637 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
638 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
639 "consoledev=ttyS0\0" \
640 "ramdiskaddr=2000000\0" \
641 "ramdiskfile=uRamdisk\0" \
643 "fdtfile=sbc8548.dtb\0"
645 #define CONFIG_NFSBOOTCOMMAND \
646 "setenv bootargs root=/dev/nfs rw " \
647 "nfsroot=$serverip:$rootpath " \
648 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
649 "console=$consoledev,$baudrate $othbootargs;" \
650 "tftp $loadaddr $bootfile;" \
651 "tftp $fdtaddr $fdtfile;" \
652 "bootm $loadaddr - $fdtaddr"
655 #define CONFIG_RAMBOOTCOMMAND \
656 "setenv bootargs root=/dev/ram rw " \
657 "console=$consoledev,$baudrate $othbootargs;" \
658 "tftp $ramdiskaddr $ramdiskfile;" \
659 "tftp $loadaddr $bootfile;" \
660 "tftp $fdtaddr $fdtfile;" \
661 "bootm $loadaddr $ramdiskaddr $fdtaddr"
663 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
665 #endif /* __CONFIG_H */