2 * Copyright 2007 Wind River Systems <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 * Joe Hamman <joe.hamman@embeddedspecialties.com>
6 * Copyright 2006 Freescale Semiconductor.
8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * SBC8641D board configuration file
32 * Make sure you change the MAC address and other network params first,
33 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
39 /* High Level Configuration Options */
40 #define CONFIG_MPC86xx 1 /* MPC86xx */
41 #define CONFIG_MPC8641 1 /* MPC8641 specific */
42 #define CONFIG_SBC8641D 1 /* SBC8641D board specific */
43 #define CONFIG_MP 1 /* support multiple processors */
44 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
45 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
48 #define CONFIG_SYS_DIAG_ADDR 0xff800000
51 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
54 * virtual address to be used for temporary mappings. There
55 * should be 128k free at this VA.
57 #define CONFIG_SYS_SCRATCH_VA 0xe8000000
59 #define CONFIG_PCI 1 /* Enable PCIE */
60 #define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */
61 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */
62 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
63 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
65 #define CONFIG_TSEC_ENET /* tsec ethernet support */
66 #define CONFIG_ENV_OVERWRITE
68 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
70 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
71 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
72 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
73 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
74 #define CONFIG_NUM_DDR_CONTROLLERS 2
75 #define CACHE_LINE_INTERLEAVING 0x20000000
76 #define PAGE_INTERLEAVING 0x21000000
77 #define BANK_INTERLEAVING 0x22000000
78 #define SUPER_BANK_INTERLEAVING 0x23000000
81 #define CONFIG_ALTIVEC 1
84 * L2CR setup -- make sure this is right for your board!
88 #define L2_ENABLE (L2CR_L2E)
90 #ifndef CONFIG_SYS_CLK_FREQ
91 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
94 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
96 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
97 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
98 #define CONFIG_SYS_MEMTEST_END 0x00400000
101 * Base addresses -- Note these are effective addresses where the
102 * actual resources get mapped (not physical addresses)
104 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
105 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
106 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
108 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
109 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
110 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
112 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
113 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
118 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
119 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
120 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
121 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
122 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
123 #define CONFIG_VERY_BIG_RAM
125 #define MPC86xx_DDR_SDRAM_CLK_CNTL
127 #define CONFIG_NUM_DDR_CONTROLLERS 2
128 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
129 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
131 #if defined(CONFIG_SPD_EEPROM)
133 * Determine DDR configuration from I2C interface.
135 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
136 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
137 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
138 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
142 * Manually set up DDR1 & DDR2 parameters
145 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
147 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
148 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
149 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
150 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
151 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
152 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
153 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
154 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
155 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
156 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
157 #define CONFIG_SYS_DDR_TIMING_1 0x38377322
158 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
159 #define CONFIG_SYS_DDR_CFG_1A 0x43008008
160 #define CONFIG_SYS_DDR_CFG_2 0x24401000
161 #define CONFIG_SYS_DDR_MODE_1 0x23c00542
162 #define CONFIG_SYS_DDR_MODE_2 0x00000000
163 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
164 #define CONFIG_SYS_DDR_INTERVAL 0x05080100
165 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
166 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
167 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
169 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
170 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
171 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
172 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
173 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
174 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
175 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
176 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
177 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
178 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
179 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
180 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
181 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
182 #define CONFIG_SYS_DDR2_CFG_2 0x24401000
183 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
184 #define CONFIG_SYS_DDR2_MODE_2 0x00000000
185 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
186 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
187 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
188 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
189 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
194 /* #define CONFIG_ID_EEPROM 1
195 #define ID_EEPROM_ADDR 0x57 */
198 * The SBC8641D contains 16MB flash space at ff000000.
200 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
203 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
204 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
207 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */
208 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
210 /* EPLD - User switches, board id, LEDs */
211 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */
212 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
214 /* Local bus SDRAM 128MB */
215 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */
216 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
217 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */
218 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
220 /* Disk on Chip (DOC) 128MB */
221 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */
222 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
225 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */
226 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
228 /* Control logic & misc peripherals */
229 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */
230 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
232 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
233 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */
235 #undef CONFIG_SYS_FLASH_CHECKSUM
236 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
237 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
238 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
239 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
241 #define CONFIG_FLASH_CFI_DRIVER
242 #define CONFIG_SYS_FLASH_CFI
243 #define CONFIG_SYS_WRITE_SWAPPED_DATA
244 #define CONFIG_SYS_FLASH_EMPTY_INFO
245 #define CONFIG_SYS_FLASH_PROTECTION
247 #undef CONFIG_CLOCKS_IN_MHZ
249 #define CONFIG_SYS_INIT_RAM_LOCK 1
250 #ifndef CONFIG_SYS_INIT_RAM_LOCK
251 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
253 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
255 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
257 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
258 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
259 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
261 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
262 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
265 #define CONFIG_CONS_INDEX 1
266 #undef CONFIG_SERIAL_SOFTWARE_FIFO
267 #define CONFIG_SYS_NS16550
268 #define CONFIG_SYS_NS16550_SERIAL
269 #define CONFIG_SYS_NS16550_REG_SIZE 1
270 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
272 #define CONFIG_SYS_BAUDRATE_TABLE \
273 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
275 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
276 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
278 /* Use the HUSH parser */
279 #define CONFIG_SYS_HUSH_PARSER
280 #ifdef CONFIG_SYS_HUSH_PARSER
281 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
285 * Pass open firmware flat tree to kernel
287 #define CONFIG_OF_LIBFDT 1
288 #define CONFIG_OF_BOARD_SETUP 1
289 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
291 #define CONFIG_SYS_64BIT_VSPRINTF 1
292 #define CONFIG_SYS_64BIT_STRTOUL 1
297 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
298 #define CONFIG_HARD_I2C /* I2C with hardware support*/
299 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
300 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
301 #define CONFIG_SYS_I2C_SLAVE 0x7F
302 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
303 #define CONFIG_SYS_I2C_OFFSET 0x3100
308 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
309 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
310 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
314 * Addresses are mapped 1-1.
316 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
317 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
318 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
319 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
320 #define CONFIG_SYS_PCI1_IO_BUS 0xe2000000
321 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS
322 #define CONFIG_SYS_PCI1_IO_VIRT CONFIG_SYS_PCI1_IO_BUS
323 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
325 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
326 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS
327 #define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BUS
328 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
329 #define CONFIG_SYS_PCI2_IO_BUS 0xe3000000
330 #define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BUS
331 #define CONFIG_SYS_PCI2_IO_VIRT CONFIG_SYS_PCI2_IO_BUS
332 #define CONFIG_SYS_PCI2_IO_SIZE 0x1000000 /* 16M */
334 #if defined(CONFIG_PCI)
336 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
338 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
340 #define CONFIG_NET_MULTI
341 #define CONFIG_PCI_PNP /* do pci plug-and-play */
343 #undef CONFIG_EEPRO100
346 #if !defined(CONFIG_PCI_PNP)
347 #define PCI_ENET0_IOADDR 0xe0000000
348 #define PCI_ENET0_MEMADDR 0xe0000000
349 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
352 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
354 #define CONFIG_DOS_PARTITION
355 #undef CONFIG_SCSI_AHCI
357 #ifdef CONFIG_SCSI_AHCI
358 #define CONFIG_SATA_ULI5288
359 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
360 #define CONFIG_SYS_SCSI_MAX_LUN 1
361 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
362 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
365 #endif /* CONFIG_PCI */
367 #if defined(CONFIG_TSEC_ENET)
369 #ifndef CONFIG_NET_MULTI
370 #define CONFIG_NET_MULTI 1
373 /* #define CONFIG_MII 1 */ /* MII PHY management */
375 #define CONFIG_TSEC1 1
376 #define CONFIG_TSEC1_NAME "eTSEC1"
377 #define CONFIG_TSEC2 1
378 #define CONFIG_TSEC2_NAME "eTSEC2"
379 #define CONFIG_TSEC3 1
380 #define CONFIG_TSEC3_NAME "eTSEC3"
381 #define CONFIG_TSEC4 1
382 #define CONFIG_TSEC4_NAME "eTSEC4"
384 #define TSEC1_PHY_ADDR 0x1F
385 #define TSEC2_PHY_ADDR 0x00
386 #define TSEC3_PHY_ADDR 0x01
387 #define TSEC4_PHY_ADDR 0x02
388 #define TSEC1_PHYIDX 0
389 #define TSEC2_PHYIDX 0
390 #define TSEC3_PHYIDX 0
391 #define TSEC4_PHYIDX 0
392 #define TSEC1_FLAGS TSEC_GIGABIT
393 #define TSEC2_FLAGS TSEC_GIGABIT
394 #define TSEC3_FLAGS TSEC_GIGABIT
395 #define TSEC4_FLAGS TSEC_GIGABIT
397 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
399 #define CONFIG_ETHPRIME "eTSEC1"
401 #endif /* CONFIG_TSEC_ENET */
404 * BAT0 2G Cacheable, non-guarded
407 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
408 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
409 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
410 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
413 * BAT1 1G Cache-inhibited, guarded
414 * 0x8000_0000 512M PCI-Express 1 Memory
415 * 0xa000_0000 512M PCI-Express 2 Memory
416 * Changed it for operating from 0xd0000000
418 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
419 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
420 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
421 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
422 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
425 * BAT2 512M Cache-inhibited, guarded
426 * 0xc000_0000 512M RapidIO Memory
428 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \
429 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
430 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
431 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
432 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
435 * BAT3 4M Cache-inhibited, guarded
436 * 0xf800_0000 4M CCSR
438 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
439 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
440 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
441 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
442 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
444 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
445 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
446 | BATL_PP_RW | BATL_CACHEINHIBIT \
447 | BATL_GUARDEDSTORAGE)
448 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
449 | BATU_BL_1M | BATU_VS | BATU_VP)
450 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
451 | BATL_PP_RW | BATL_CACHEINHIBIT)
452 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
456 * BAT4 32M Cache-inhibited, guarded
457 * 0xe200_0000 16M PCI-Express 1 I/O
458 * 0xe300_0000 16M PCI-Express 2 I/0
459 * Note that this is at 0xe0000000
461 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
462 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
463 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
464 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
465 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
468 * BAT5 128K Cacheable, non-guarded
469 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
471 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
472 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
473 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
474 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
477 * BAT6 32M Cache-inhibited, guarded
478 * 0xfe00_0000 32M FLASH
480 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
481 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
482 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
483 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
484 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
486 /* Map the last 1M of flash where we're running from reset */
487 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
488 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
489 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
490 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
492 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
494 #define CONFIG_SYS_DBAT7L 0x00000000
495 #define CONFIG_SYS_DBAT7U 0x00000000
496 #define CONFIG_SYS_IBAT7L 0x00000000
497 #define CONFIG_SYS_IBAT7U 0x00000000
502 #define CONFIG_ENV_IS_IN_FLASH 1
503 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
504 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
505 #define CONFIG_ENV_SIZE 0x2000
507 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
508 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
510 #include <config_cmd_default.h>
511 #define CONFIG_CMD_PING
512 #define CONFIG_CMD_I2C
513 #define CONFIG_CMD_REGINFO
515 #if defined(CONFIG_PCI)
516 #define CONFIG_CMD_PCI
519 #undef CONFIG_WATCHDOG /* watchdog disabled */
522 * Miscellaneous configurable options
524 #define CONFIG_SYS_LONGHELP /* undef to save memory */
525 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
526 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
528 #if defined(CONFIG_CMD_KGDB)
529 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
531 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
534 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
535 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
536 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
537 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
540 * For booting Linux, the board info and command line data
541 * have to be in the first 8 MB of memory, since this is
542 * the maximum mapped by the Linux kernel during initialization.
544 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
546 /* Cache Configuration */
547 #define CONFIG_SYS_DCACHE_SIZE 32768
548 #define CONFIG_SYS_CACHELINE_SIZE 32
549 #if defined(CONFIG_CMD_KGDB)
550 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
554 * Internal Definitions
558 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
559 #define BOOTFLAG_WARM 0x02 /* Software reboot */
561 #if defined(CONFIG_CMD_KGDB)
562 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
563 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
567 * Environment Configuration
570 /* The mac addresses for all ethernet interface */
571 #if defined(CONFIG_TSEC_ENET)
572 #define CONFIG_ETHADDR 02:E0:0C:00:00:01
573 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
574 #define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
575 #define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
578 #define CONFIG_HAS_ETH0 1
579 #define CONFIG_HAS_ETH1 1
580 #define CONFIG_HAS_ETH2 1
581 #define CONFIG_HAS_ETH3 1
583 #define CONFIG_IPADDR 192.168.0.50
585 #define CONFIG_HOSTNAME sbc8641d
586 #define CONFIG_ROOTPATH /opt/eldk/ppc_74xx
587 #define CONFIG_BOOTFILE uImage
589 #define CONFIG_SERVERIP 192.168.0.2
590 #define CONFIG_GATEWAYIP 192.168.0.1
591 #define CONFIG_NETMASK 255.255.255.0
593 /* default location for tftp and bootm */
594 #define CONFIG_LOADADDR 1000000
596 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
597 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
599 #define CONFIG_BAUDRATE 115200
601 #define CONFIG_EXTRA_ENV_SETTINGS \
603 "consoledev=ttyS0\0" \
604 "ramdiskaddr=2000000\0" \
605 "ramdiskfile=uRamdisk\0" \
607 "dtbfile=sbc8641d.dtb\0" \
608 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
609 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
612 #define CONFIG_NFSBOOTCOMMAND \
613 "setenv bootargs root=/dev/nfs rw " \
614 "nfsroot=$serverip:$rootpath " \
615 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
616 "console=$consoledev,$baudrate $othbootargs;" \
617 "tftp $loadaddr $bootfile;" \
618 "tftp $dtbaddr $dtbfile;" \
619 "bootm $loadaddr - $dtbaddr"
621 #define CONFIG_RAMBOOTCOMMAND \
622 "setenv bootargs root=/dev/ram rw " \
623 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
624 "console=$consoledev,$baudrate $othbootargs;" \
625 "tftp $ramdiskaddr $ramdiskfile;" \
626 "tftp $loadaddr $bootfile;" \
627 "tftp $dtbaddr $dtbfile;" \
628 "bootm $loadaddr $ramdiskaddr $dtbaddr"
630 #define CONFIG_FLASHBOOTCOMMAND \
631 "setenv bootargs root=/dev/ram rw " \
632 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
633 "console=$consoledev,$baudrate $othbootargs;" \
634 "bootm ffd00000 ffb00000 ffa00000"
636 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
638 #endif /* __CONFIG_H */