2 * Configuation settings for the sh7757lcr board
4 * Copyright (C) 2011 Renesas Solutions Corp.
6 * SPDX-License-Identifier: GPL-2.0+
12 #define CONFIG_CPU_SH7757 1
13 #define CONFIG_SH7757LCR_DDR_ECC 1
15 #define CONFIG_DISPLAY_BOARDINFO
16 #undef CONFIG_SHOW_BOOT_PROGRESS
19 #define SH7757LCR_SDRAM_BASE (0x80000000)
20 #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
21 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
22 #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
24 #define CONFIG_SYS_LONGHELP
25 #define CONFIG_SYS_PBSIZE 256
26 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
29 #define CONFIG_CONS_SCIF2 1
31 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
32 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
34 #undef CONFIG_SYS_ALT_MEMTEST
35 #undef CONFIG_SYS_MEMTEST_SCRATCH
36 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
38 #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
39 #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
40 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
41 (128 + 16) * 1024 * 1024)
43 #define CONFIG_SYS_MONITOR_BASE 0x00000000
44 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
45 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
46 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
49 #define CONFIG_SH_ETHER_USE_PORT 0
50 #define CONFIG_SH_ETHER_PHY_ADDR 1
51 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
52 #define CONFIG_BITBANGMII
53 #define CONFIG_BITBANGMII_MULTI
54 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
56 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
57 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
58 #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
59 #define SH7757LCR_ETHERNET_MAC_SIZE 17
60 #define SH7757LCR_ETHERNET_NUM_CH 2
63 #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
66 #define CONFIG_SH_SPI 1
67 #define CONFIG_SH_SPI_BASE 0xfe002000
70 #define CONFIG_SH_MMCIF 1
71 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000
72 #define CONFIG_SH_MMCIF_CLK 48000000
75 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
76 #define SH7757LCR_GRA_OFFSET 0x1f000000
77 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
78 #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
79 #define SH7757LCR_PCIEBRG_ADDR 0x00090000
80 #define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
83 #define CONFIG_ENV_IS_EMBEDDED
84 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
85 #define CONFIG_ENV_ADDR (0x00080000)
86 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
87 #define CONFIG_ENV_OVERWRITE 1
88 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
89 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
90 #define CONFIG_EXTRA_ENV_SETTINGS \
91 "netboot=bootp; bootm\0"
94 #define CONFIG_SYS_CLK_FREQ 48000000
95 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
96 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
97 #define CONFIG_SYS_TMU_CLK_DIV 4
98 #endif /* __SH7757LCR_H */