2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
7 #define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
9 #define CONFIG_SYS_GENERIC_BOARD
11 /* Virtual target or real hardware */
12 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
14 #define CONFIG_SYS_THUMB_BUILD
17 * High level configuration
19 #define CONFIG_DISPLAY_CPUINFO
20 #define CONFIG_DISPLAY_BOARDINFO_LATE
21 #define CONFIG_ARCH_EARLY_INIT_R
22 #define CONFIG_SYS_NO_FLASH
26 #define CONFIG_OF_LIBFDT
27 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
32 * Memory configurations
34 #define CONFIG_NR_DRAM_BANKS 1
35 #define PHYS_SDRAM_1 0x0
36 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
37 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
38 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
40 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
41 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE)
42 #define CONFIG_SYS_INIT_SP_ADDR \
43 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
44 GENERATED_GBL_DATA_SIZE)
46 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
47 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
48 #define CONFIG_SYS_TEXT_BASE 0x08000040
50 #define CONFIG_SYS_TEXT_BASE 0x01000040
54 * U-Boot general configurations
56 #define CONFIG_SYS_LONGHELP
57 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
58 #define CONFIG_SYS_PBSIZE \
59 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
60 /* Print buffer size */
61 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
62 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
63 /* Boot argument buffer size */
64 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
65 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
66 #define CONFIG_CMDLINE_EDITING /* Command history etc */
67 #define CONFIG_SYS_HUSH_PARSER
72 #define CONFIG_SYS_ARM_CACHE_WRITEALLOC
73 #define CONFIG_SYS_CACHELINE_SIZE 32
74 #define CONFIG_SYS_L2_PL310
75 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
78 * EPCS/EPCQx1 Serial Flash Controller
80 #ifdef CONFIG_ALTERA_SPI
81 #define CONFIG_CMD_SPI
83 #define CONFIG_SF_DEFAULT_SPEED 30000000
84 #define CONFIG_SPI_FLASH_STMICRO
85 #define CONFIG_SPI_FLASH_BAR
87 * The base address is configurable in QSys, each board must specify the
88 * base address based on it's particular FPGA configuration. Please note
89 * that the address here is incremented by 0x400 from the Base address
90 * selected in QSys, since the SPI registers are at offset +0x400.
91 * #define CONFIG_SYS_SPI_BASE 0xff240400
96 * Ethernet on SoC (EMAC)
98 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
99 #define CONFIG_DW_ALTDESCRIPTOR
101 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
102 #define CONFIG_PHYLIB
103 #define CONFIG_PHY_GIGE
109 #ifdef CONFIG_CMD_FPGA
111 #define CONFIG_FPGA_ALTERA
112 #define CONFIG_FPGA_SOCFPGA
113 #define CONFIG_FPGA_COUNT 1
119 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
120 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
121 #define CONFIG_SYS_TIMER_COUNTS_DOWN
122 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
123 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
124 #define CONFIG_SYS_TIMER_RATE 2400000
126 #define CONFIG_SYS_TIMER_RATE 25000000
132 #ifdef CONFIG_HW_WATCHDOG
133 #define CONFIG_DESIGNWARE_WATCHDOG
134 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
135 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
136 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000
142 #ifdef CONFIG_CMD_MMC
144 #define CONFIG_BOUNCE_BUFFER
145 #define CONFIG_GENERIC_MMC
147 #define CONFIG_SOCFPGA_DWMMC
148 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
149 #define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
150 #define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
152 /* using smaller max blk cnt to avoid flooding the limited stack we have */
153 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
159 #define CONFIG_SYS_I2C
160 #define CONFIG_SYS_I2C_DW
161 #define CONFIG_SYS_I2C_BUS_MAX 4
162 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
163 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
164 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
165 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
166 /* Using standard mode which the speed up to 100Kb/s */
167 #define CONFIG_SYS_I2C_SPEED 100000
168 #define CONFIG_SYS_I2C_SPEED1 100000
169 #define CONFIG_SYS_I2C_SPEED2 100000
170 #define CONFIG_SYS_I2C_SPEED3 100000
171 /* Address of device when used as slave */
172 #define CONFIG_SYS_I2C_SLAVE 0x02
173 #define CONFIG_SYS_I2C_SLAVE1 0x02
174 #define CONFIG_SYS_I2C_SLAVE2 0x02
175 #define CONFIG_SYS_I2C_SLAVE3 0x02
177 /* Clock supplied to I2C controller in unit of MHz */
178 unsigned int cm_get_l4_sp_clk_hz(void);
179 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
181 #define CONFIG_CMD_I2C
186 #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
187 #define CONFIG_CADENCE_QSPI
188 /* Enable multiple SPI NOR flash manufacturers */
189 #define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
190 #define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
191 #define CONFIG_SPI_FLASH_MTD
192 /* QSPI reference clock */
194 unsigned int cm_get_qspi_controller_clk_hz(void);
195 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
197 #define CONFIG_CQSPI_DECODER 0
198 #define CONFIG_CMD_SF
201 #ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */
202 #define CONFIG_DESIGNWARE_SPI
203 #define CONFIG_CMD_SPI
209 #define CONFIG_SYS_NS16550
210 #define CONFIG_SYS_NS16550_SERIAL
211 #define CONFIG_SYS_NS16550_REG_SIZE -4
212 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
213 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
214 #define CONFIG_SYS_NS16550_CLK 1000000
216 #define CONFIG_SYS_NS16550_CLK 100000000
218 #define CONFIG_CONS_INDEX 1
219 #define CONFIG_BAUDRATE 115200
224 #ifdef CONFIG_CMD_USB
225 #define CONFIG_USB_DWC2
226 #define CONFIG_USB_STORAGE
228 * NOTE: User must define either of the following to select which
229 * of the two USB controllers available on SoCFPGA to use.
230 * The DWC2 driver doesn't support multiple USB controllers.
231 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS
232 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
237 * USB Gadget (DFU, UMS)
239 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
240 #define CONFIG_USB_GADGET
241 #define CONFIG_USB_GADGET_S3C_UDC_OTG
242 #define CONFIG_USB_GADGET_DUALSPEED
243 #define CONFIG_USB_GADGET_VBUS_DRAW 2
245 /* USB Composite download gadget - g_dnl */
246 #define CONFIG_USBDOWNLOAD_GADGET
247 #define CONFIG_USB_GADGET_MASS_STORAGE
249 #define CONFIG_DFU_FUNCTION
250 #define CONFIG_DFU_MMC
251 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
252 #define DFU_DEFAULT_POLL_TIMEOUT 300
255 #define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */
256 #define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */
257 #define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
258 #define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM
259 #ifndef CONFIG_G_DNL_MANUFACTURER
260 #define CONFIG_G_DNL_MANUFACTURER "Altera"
267 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
268 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
269 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
270 #define CONFIG_ENV_IS_NOWHERE
271 #define CONFIG_ENV_SIZE 4096
276 * SRAM Memory layout:
278 * 0xFFFF_0000 ...... Start of SRAM
279 * 0xFFFF_xxxx ...... Top of stack (grows down)
280 * 0xFFFF_yyyy ...... Malloc area
281 * 0xFFFF_zzzz ...... Global Data
282 * 0xFFFF_FF00 ...... End of SRAM
284 #define CONFIG_SPL_FRAMEWORK
285 #define CONFIG_SPL_BOARD_INIT
286 #define CONFIG_SPL_RAM_DEVICE
287 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
288 #define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR
289 #define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024)
290 #define CONFIG_SPL_MAX_SIZE (64 * 1024)
292 #define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
293 #define CONFIG_CRC32_VERIFY
295 /* Linker script for SPL */
296 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-socfpga/u-boot-spl.lds"
298 #define CONFIG_SPL_LIBCOMMON_SUPPORT
299 #define CONFIG_SPL_LIBGENERIC_SUPPORT
300 #define CONFIG_SPL_WATCHDOG_SUPPORT
301 #define CONFIG_SPL_SERIAL_SUPPORT
306 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
308 #ifdef CONFIG_SPL_BUILD
309 #undef CONFIG_PARTITIONS
312 #endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */