2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
7 #define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
9 #define CONFIG_SYS_GENERIC_BOARD
11 /* Virtual target or real hardware */
12 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
14 #define CONFIG_SYS_THUMB_BUILD
17 * High level configuration
19 #define CONFIG_DISPLAY_CPUINFO
20 #define CONFIG_DISPLAY_BOARDINFO_LATE
21 #define CONFIG_ARCH_MISC_INIT
22 #define CONFIG_ARCH_EARLY_INIT_R
23 #define CONFIG_SYS_NO_FLASH
26 #define CONFIG_CRC32_VERIFY
29 #define CONFIG_OF_LIBFDT
30 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
32 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
35 * Memory configurations
37 #define CONFIG_NR_DRAM_BANKS 1
38 #define PHYS_SDRAM_1 0x0
39 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
40 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
41 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
43 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
44 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
45 #define CONFIG_SYS_INIT_SP_OFFSET \
46 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
47 #define CONFIG_SYS_INIT_SP_ADDR \
48 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
50 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
51 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
52 #define CONFIG_SYS_TEXT_BASE 0x08000040
54 #define CONFIG_SYS_TEXT_BASE 0x01000040
58 * U-Boot general configurations
60 #define CONFIG_SYS_LONGHELP
61 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
62 #define CONFIG_SYS_PBSIZE \
63 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
64 /* Print buffer size */
65 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
66 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
67 /* Boot argument buffer size */
68 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
69 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
70 #define CONFIG_CMDLINE_EDITING /* Command history etc */
71 #define CONFIG_SYS_HUSH_PARSER
76 #define CONFIG_SYS_CACHELINE_SIZE 32
77 #define CONFIG_SYS_L2_PL310
78 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
83 #define CONFIG_ALTERA_SDRAM
86 * EPCS/EPCQx1 Serial Flash Controller
88 #ifdef CONFIG_ALTERA_SPI
89 #define CONFIG_CMD_SPI
91 #define CONFIG_SF_DEFAULT_SPEED 30000000
92 #define CONFIG_SPI_FLASH_STMICRO
93 #define CONFIG_SPI_FLASH_BAR
95 * The base address is configurable in QSys, each board must specify the
96 * base address based on it's particular FPGA configuration. Please note
97 * that the address here is incremented by 0x400 from the Base address
98 * selected in QSys, since the SPI registers are at offset +0x400.
99 * #define CONFIG_SYS_SPI_BASE 0xff240400
104 * Ethernet on SoC (EMAC)
106 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
107 #define CONFIG_DW_ALTDESCRIPTOR
109 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
110 #define CONFIG_PHYLIB
111 #define CONFIG_PHY_GIGE
117 #ifdef CONFIG_CMD_FPGA
119 #define CONFIG_FPGA_ALTERA
120 #define CONFIG_FPGA_SOCFPGA
121 #define CONFIG_FPGA_COUNT 1
127 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
128 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
129 #define CONFIG_SYS_TIMER_COUNTS_DOWN
130 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
131 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
132 #define CONFIG_SYS_TIMER_RATE 2400000
134 #define CONFIG_SYS_TIMER_RATE 25000000
140 #ifdef CONFIG_HW_WATCHDOG
141 #define CONFIG_DESIGNWARE_WATCHDOG
142 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
143 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
144 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000
150 #ifdef CONFIG_CMD_MMC
152 #define CONFIG_BOUNCE_BUFFER
153 #define CONFIG_GENERIC_MMC
155 #define CONFIG_SOCFPGA_DWMMC
156 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
157 #define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
158 #define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
160 /* using smaller max blk cnt to avoid flooding the limited stack we have */
161 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
167 #define CONFIG_SYS_I2C
168 #define CONFIG_SYS_I2C_DW
169 #define CONFIG_SYS_I2C_BUS_MAX 4
170 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
171 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
172 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
173 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
174 /* Using standard mode which the speed up to 100Kb/s */
175 #define CONFIG_SYS_I2C_SPEED 100000
176 #define CONFIG_SYS_I2C_SPEED1 100000
177 #define CONFIG_SYS_I2C_SPEED2 100000
178 #define CONFIG_SYS_I2C_SPEED3 100000
179 /* Address of device when used as slave */
180 #define CONFIG_SYS_I2C_SLAVE 0x02
181 #define CONFIG_SYS_I2C_SLAVE1 0x02
182 #define CONFIG_SYS_I2C_SLAVE2 0x02
183 #define CONFIG_SYS_I2C_SLAVE3 0x02
185 /* Clock supplied to I2C controller in unit of MHz */
186 unsigned int cm_get_l4_sp_clk_hz(void);
187 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
189 #define CONFIG_CMD_I2C
194 #define CONFIG_CADENCE_QSPI
195 /* Enable multiple SPI NOR flash manufacturers */
196 #define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
197 #define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
198 #ifndef CONFIG_SPL_BUILD
199 #define CONFIG_SPI_FLASH_MTD
200 #define CONFIG_CMD_MTDPARTS
201 #define CONFIG_MTD_DEVICE
202 #define CONFIG_MTD_PARTITIONS
203 #define MTDIDS_DEFAULT "nor0=ff705000.spi"
205 /* QSPI reference clock */
207 unsigned int cm_get_qspi_controller_clk_hz(void);
208 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
210 #define CONFIG_CQSPI_DECODER 0
211 #define CONFIG_CMD_SF
212 #define CONFIG_SPI_FLASH_BAR
215 * Designware SPI support
217 #define CONFIG_DESIGNWARE_SPI
218 #define CONFIG_CMD_SPI
223 #define CONFIG_SYS_NS16550
224 #define CONFIG_SYS_NS16550_SERIAL
225 #define CONFIG_SYS_NS16550_REG_SIZE -4
226 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
227 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
228 #define CONFIG_SYS_NS16550_CLK 1000000
230 #define CONFIG_SYS_NS16550_CLK 100000000
232 #define CONFIG_CONS_INDEX 1
233 #define CONFIG_BAUDRATE 115200
238 #ifdef CONFIG_CMD_USB
239 #define CONFIG_USB_DWC2
240 #define CONFIG_USB_STORAGE
242 * NOTE: User must define either of the following to select which
243 * of the two USB controllers available on SoCFPGA to use.
244 * The DWC2 driver doesn't support multiple USB controllers.
245 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS
246 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
251 * USB Gadget (DFU, UMS)
253 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
254 #define CONFIG_USB_GADGET
255 #define CONFIG_USB_GADGET_S3C_UDC_OTG
256 #define CONFIG_USB_GADGET_DUALSPEED
257 #define CONFIG_USB_GADGET_VBUS_DRAW 2
259 /* USB Composite download gadget - g_dnl */
260 #define CONFIG_USB_GADGET_DOWNLOAD
261 #define CONFIG_USB_FUNCTION_MASS_STORAGE
263 #define CONFIG_USB_FUNCTION_DFU
264 #define CONFIG_DFU_MMC
265 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
266 #define DFU_DEFAULT_POLL_TIMEOUT 300
269 #define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */
270 #define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */
271 #define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
272 #define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM
273 #ifndef CONFIG_G_DNL_MANUFACTURER
274 #define CONFIG_G_DNL_MANUFACTURER "Altera"
281 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
282 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
283 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
284 #define CONFIG_ENV_SIZE 4096
289 * SRAM Memory layout:
291 * 0xFFFF_0000 ...... Start of SRAM
292 * 0xFFFF_xxxx ...... Top of stack (grows down)
293 * 0xFFFF_yyyy ...... Malloc area
294 * 0xFFFF_zzzz ...... Global Data
295 * 0xFFFF_FF00 ...... End of SRAM
297 #define CONFIG_SPL_FRAMEWORK
298 #define CONFIG_SPL_RAM_DEVICE
299 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
300 #define CONFIG_SPL_MAX_SIZE (64 * 1024)
301 #ifdef CONFIG_SPL_BUILD
302 #define CONFIG_SYS_MALLOC_SIMPLE
305 #define CONFIG_SPL_LIBCOMMON_SUPPORT
306 #define CONFIG_SPL_LIBGENERIC_SUPPORT
307 #define CONFIG_SPL_WATCHDOG_SUPPORT
308 #define CONFIG_SPL_SERIAL_SUPPORT
309 #define CONFIG_SPL_MMC_SUPPORT
310 #define CONFIG_SPL_SPI_SUPPORT
312 /* SPL SDMMC boot support */
313 #ifdef CONFIG_SPL_MMC_SUPPORT
314 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
315 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
316 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
317 #define CONFIG_SPL_LIBDISK_SUPPORT
319 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3
320 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */
321 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
325 /* SPL QSPI boot support */
326 #ifdef CONFIG_SPL_SPI_SUPPORT
327 #define CONFIG_DM_SEQ_ALIAS 1
328 #define CONFIG_SPL_SPI_FLASH_SUPPORT
329 #define CONFIG_SPL_SPI_LOAD
330 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
336 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
338 #endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */