3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
5 * Wolfgang Denk <wd@denx.de>
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
10 * SPDX-License-Identifier: GPL-2.0+
20 /* High Level Configuration Options */
21 #define CONFIG_SOCRATES 1
23 #define CONFIG_PCI_INDIRECT_BRIDGE
25 #define CONFIG_TSEC_ENET /* tsec ethernet support */
27 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
28 #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
31 * Only possible on E500 Version 2 or newer cores.
33 #define CONFIG_ENABLE_36BIT_PHYS 1
38 * Two valid values are:
42 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
43 * is likely the desired value here, so that is now the default.
44 * The board, however, can run at 66MHz. In any event, this value
45 * must match the settings of some switches. Details can be found
46 * in the README.mpc85xxads.
49 #ifndef CONFIG_SYS_CLK_FREQ
50 #define CONFIG_SYS_CLK_FREQ 66666666
54 * These can be toggled for performance analysis, otherwise use default.
56 #define CONFIG_L2_CACHE /* toggle L2 cache */
57 #define CONFIG_BTB /* toggle branch predition */
59 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
61 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
62 #define CONFIG_SYS_MEMTEST_START 0x00400000
63 #define CONFIG_SYS_MEMTEST_END 0x00C00000
65 #define CONFIG_SYS_CCSRBAR 0xE0000000
66 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
69 #undef CONFIG_FSL_DDR_INTERACTIVE
70 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
71 #define CONFIG_DDR_SPD
73 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
74 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
76 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
77 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
78 #define CONFIG_VERY_BIG_RAM
80 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
81 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
83 /* I2C addresses of SPD EEPROMs */
84 #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
86 #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
88 /* Hardcoded values, to use instead of SPD */
89 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
90 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
91 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
92 #define CONFIG_SYS_DDR_TIMING_1 0x3935D322
93 #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
94 #define CONFIG_SYS_DDR_MODE 0x00480432
95 #define CONFIG_SYS_DDR_INTERVAL 0x030C0100
96 #define CONFIG_SYS_DDR_CONFIG_2 0x04400000
97 #define CONFIG_SYS_DDR_CONFIG 0xC3008000
98 #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
99 #define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
102 * Flash on the LocalBus
104 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
106 #define CONFIG_SYS_FLASH0 0xFE000000
107 #define CONFIG_SYS_FLASH1 0xFC000000
108 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
110 #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
111 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
113 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
114 #define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
115 #define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
116 #define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
118 #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
119 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
121 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
122 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
123 #undef CONFIG_SYS_FLASH_CHECKSUM
124 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
125 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
129 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
130 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
131 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
132 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
134 #define CONFIG_SYS_INIT_RAM_LOCK 1
135 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
136 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
138 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
139 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
141 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
142 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
145 #define CONFIG_SYS_FPGA_BASE 0xc0000000
146 #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
147 #define CONFIG_SYS_HMI_BASE 0xc0010000
148 #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
149 #define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
151 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
152 #define CONFIG_SYS_MAX_NAND_DEVICE 1
155 #define CONFIG_SYS_LIME_BASE 0xc8000000
156 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
157 #define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
158 #define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
160 #define CONFIG_VIDEO_MB862xx
161 #define CONFIG_VIDEO_MB862xx_ACCEL
162 #define CONFIG_VIDEO_LOGO
163 #define CONFIG_VIDEO_BMP_LOGO
164 #define VIDEO_FB_16BPP_PIXEL_SWAP
165 #define VIDEO_FB_16BPP_WORD_SWAP
166 #define CONFIG_SPLASH_SCREEN
167 #define CONFIG_VIDEO_BMP_GZIP
168 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
170 /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
171 #define CONFIG_SYS_MB862xx_CCF 0x10000
172 /* SDRAM parameter */
173 #define CONFIG_SYS_MB862xx_MMR 0x4157BA63
177 #define CONFIG_CONS_INDEX 1
178 #define CONFIG_SYS_NS16550_SERIAL
179 #define CONFIG_SYS_NS16550_REG_SIZE 1
180 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
182 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
183 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
185 #define CONFIG_SYS_BAUDRATE_TABLE \
186 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
191 #define CONFIG_SYS_I2C
192 #define CONFIG_SYS_I2C_FSL
193 #define CONFIG_SYS_FSL_I2C_SPEED 102124
194 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
195 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
196 #define CONFIG_SYS_FSL_I2C2_SPEED 102124
197 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
198 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
201 #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
202 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */
204 /* I2C W83782G HW-Monitoring IC */
205 #define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */
207 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
211 * Memory space is mapped 1-1.
213 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
215 /* PCI is clocked by the external source at 33 MHz */
216 #define CONFIG_PCI_CLK_FREQ 33000000
217 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
218 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
219 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
220 #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
221 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
222 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
224 #if defined(CONFIG_PCI)
225 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
226 #endif /* CONFIG_PCI */
228 #define CONFIG_MII 1 /* MII PHY management */
229 #define CONFIG_TSEC1 1
230 #define CONFIG_TSEC1_NAME "TSEC0"
231 #define CONFIG_TSEC3 1
232 #define CONFIG_TSEC3_NAME "TSEC1"
233 #undef CONFIG_MPC85XX_FEC
235 #define TSEC1_PHY_ADDR 0
236 #define TSEC3_PHY_ADDR 1
238 #define TSEC1_PHYIDX 0
239 #define TSEC3_PHYIDX 0
240 #define TSEC1_FLAGS TSEC_GIGABIT
241 #define TSEC3_FLAGS TSEC_GIGABIT
243 /* Options are: TSEC[0,1] */
244 #define CONFIG_ETHPRIME "TSEC0"
246 #define CONFIG_HAS_ETH0
247 #define CONFIG_HAS_ETH1
252 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
253 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
254 #define CONFIG_ENV_SIZE 0x4000
255 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
256 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
258 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
259 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
261 #define CONFIG_TIMESTAMP /* Print image info with ts */
266 #define CONFIG_BOOTP_BOOTFILESIZE
268 #undef CONFIG_WATCHDOG /* watchdog disabled */
271 * Miscellaneous configurable options
273 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
276 * For booting Linux, the board info and command line data
277 * have to be in the first 8 MB of memory, since this is
278 * the maximum mapped by the Linux kernel during initialization.
280 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
282 #if defined(CONFIG_CMD_KGDB)
283 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
286 #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
289 #define CONFIG_PREBOOT "echo;" \
290 "echo Welcome on the ABB Socrates Board;" \
293 #define CONFIG_EXTRA_ENV_SETTINGS \
296 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
297 "bootfile=/home/tftp/syscon3/uImage\0" \
298 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
299 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
300 "uboot_addr=FFFA0000\0" \
301 "kernel_addr=FE000000\0" \
302 "fdt_addr=FE1E0000\0" \
303 "ramdisk_addr=FE200000\0" \
304 "fdt_addr_r=B00000\0" \
305 "kernel_addr_r=200000\0" \
306 "ramdisk_addr_r=400000\0" \
307 "rootpath=/opt/eldk/ppc_85xxDP\0" \
308 "ramargs=setenv bootargs root=/dev/ram rw\0" \
309 "nfsargs=setenv bootargs root=/dev/nfs rw " \
310 "nfsroot=$serverip:$rootpath\0" \
311 "addcons=setenv bootargs $bootargs " \
312 "console=$consdev,$baudrate\0" \
313 "addip=setenv bootargs $bootargs " \
314 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
315 ":$hostname:$netdev:off panic=1\0" \
316 "boot_nor=run ramargs addcons;" \
317 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
318 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
319 "tftp ${fdt_addr_r} ${fdt_file}; " \
320 "run nfsargs addip addcons;" \
321 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
322 "update_uboot=tftp 100000 ${uboot_file};" \
323 "protect off fffa0000 ffffffff;" \
324 "era fffa0000 ffffffff;" \
325 "cp.b 100000 fffa0000 ${filesize};" \
326 "setenv filesize;saveenv\0" \
327 "update_kernel=tftp 100000 ${bootfile};" \
328 "era fe000000 fe1dffff;" \
329 "cp.b 100000 fe000000 ${filesize};" \
330 "setenv filesize;saveenv\0" \
331 "update_fdt=tftp 100000 ${fdt_file};" \
332 "era fe1e0000 fe1fffff;" \
333 "cp.b 100000 fe1e0000 ${filesize};" \
334 "setenv filesize;saveenv\0" \
335 "update_initrd=tftp 100000 ${initrd_file};" \
336 "era fe200000 fe9fffff;" \
337 "cp.b 100000 fe200000 ${filesize};" \
338 "setenv filesize;saveenv\0" \
339 "clean_data=era fea00000 fff5ffff\0" \
340 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
341 "load_usb=usb start;" \
342 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
343 "boot_usb=run load_usb usbargs addcons;" \
344 "bootm ${kernel_addr_r} - ${fdt_addr};" \
345 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
347 #define CONFIG_BOOTCOMMAND "run boot_nor"
349 /* pass open firmware flat tree */
352 #define CONFIG_USB_OHCI_NEW 1
353 #define CONFIG_PCI_OHCI 1
354 #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
355 #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
356 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
357 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
358 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
360 #endif /* __CONFIG_H */