3 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
31 #define CONFIG_MPC8220 1
32 #define CONFIG_SORCERY 1 /* Sorcery board */
34 /* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
35 determine the CPU speed. */
36 #define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */
37 #define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
39 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
40 #define BOOTFLAG_WARM 0x02 /* Software reboot */
42 #define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
44 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
45 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
49 * Serial console configuration
51 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC */
53 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
54 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
59 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
78 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
79 #include <cmd_confdefs.h>
84 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
85 #define CONFIG_HOSTNAME sorcery
87 #define CONFIG_PREBOOT "echo;" \
88 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
91 #undef CONFIG_BOOTARGS
93 #define CONFIG_EXTRA_ENV_SETTINGS \
95 "nfsargs=setenv bootargs root=/dev/nfs rw " \
96 "nfsroot=$serverip:$rootpath\0" \
97 "ramargs=setenv bootargs root=/dev/ram rw\0" \
98 "addip=setenv bootargs $bootargs " \
99 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
100 ":$hostname:$netdev:off panic=1\0" \
101 "flash_nfs=run nfsargs addip;" \
102 "bootm $kernel_addr\0" \
103 "flash_self=run ramargs addip;" \
104 "bootm $kernel_addr $ramdisk_addr\0" \
105 "net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \
106 "rootpath=/opt/eldk/ppc_82xx\0" \
107 "bootfile=/tftpboot/sorcery/uImage\0" \
108 "kernel_addr=FFE00000\0" \
109 "ramdisk_addr=FFB00000\0" \
111 #define CONFIG_BOOTCOMMAND "run flash_self"
113 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
115 #define CONFIG_NET_MULTI
120 #define CONFIG_HARD_I2C 1
121 #define CFG_I2C_MODULE 1
122 #define CFG_I2C_SPEED 100000 /* 100 kHz */
123 #define CFG_I2C_SLAVE 0x7F
125 /* Use the HUSH parser */
126 #define CFG_HUSH_PARSER
127 #ifdef CFG_HUSH_PARSER
128 #define CFG_PROMPT_HUSH_PS2 "> "
132 * Flexbus Chipselect configuration
133 * Beware: Some CS# seem to be mandatory (if these CS# are not set,
134 * board can hang-up in unpredictable place).
135 * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
139 #define CFG_CS0_BASE 0xf800
140 #define CFG_CS0_MASK 0x08000000 /* 128 MB (two chips) */
142 /* Workaround of hang-up after setting ctrl register for flash
143 After reset this register has value 0x003ffd80, which differs
144 from suggested only by the number of wait states.
145 #define CFG_CS0_CTRL 0x003f1580
149 #define CFG_CS1_BASE 0xf100
150 #define CFG_CS1_MASK 0x00080000 /* 512K */
151 #define CFG_CS1_CTRL 0x003ffd40 /* 8bit port size? */
153 /* Atlas2 + Gemini */
154 /* This CS# is mandatory? */
155 #define CFG_CS2_BASE 0xf10A
156 #define CFG_CS2_MASK 0x00020000 /* 2x64K*/
157 #define CFG_CS2_CTRL 0x003ffd00 /* 32bit port size? */
160 /* This CS# is mandatory? */
161 #define CFG_CS3_BASE 0xf10C
162 #define CFG_CS3_MASK 0x00010000 /* 64K */
163 #define CFG_CS3_CTRL 0x003ffd40 /* 8Bit port size */
165 /* Foreign interface */
166 #define CFG_CS4_BASE 0xF10D
167 #define CFG_CS4_MASK 0x00010000 /* 64K */
168 #define CFG_CS4_CTRL 0x003ffd80 /* 16bit port size */
171 /* This CS# is mandatory? */
172 #define CFG_CS5_BASE 0xF108
173 #define CFG_CS5_MASK 0x00010000
174 #define CFG_CS5_CTRL 0x003ffd80 /* 16bit port size */
176 #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
177 #define CFG_FLASH_BASE CFG_FLASH0_BASE
179 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks (actually 4? (at least 2)) */
180 #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip (actually 256) */
183 #define PHYS_AMD_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
185 #define CFG_FLASH_CFI_DRIVER
186 #define CFG_FLASH_CFI
187 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \
188 CFG_FLASH_BASE+0x04000000 } /* two banks */
191 * Environment settings
193 #define CFG_ENV_IS_IN_FLASH 1
194 #define CFG_ENV_ADDR (CFG_FLASH0_BASE)
195 #define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE
196 #define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
198 #define CONFIG_ENV_OVERWRITE 1
200 #if defined CFG_ENV_IS_IN_FLASH
201 #undef CFG_ENV_IS_IN_NVRAM
202 #undef CFG_ENV_IS_IN_EEPROM
203 #elif defined CFG_ENV_IS_IN_NVRAM
204 #undef CFG_ENV_IS_IN_FLASH
205 #undef CFG_ENV_IS_IN_EEPROM
206 #elif defined CFG_ENV_IS_IN_EEPROM
207 #undef CFG_ENV_IS_IN_NVRAM
208 #undef CFG_ENV_IS_IN_FLASH
214 #define CFG_MBAR 0xF0000000
215 #define CFG_SDRAM_BASE 0x00000000
216 #define CFG_DEFAULT_MBAR 0x80000000
217 #define CFG_SRAM_BASE (CFG_MBAR + 0x20000)
218 #define CFG_SRAM_SIZE 0x8000
220 /* Use SRAM until RAM will be available */
221 #define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000)
222 #define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
224 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
225 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
226 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
228 #define CFG_MONITOR_BASE TEXT_BASE
229 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
230 # define CFG_RAMBOOT 1
233 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
234 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
235 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
237 /* SDRAM configuration (for SPD) */
238 #define CFG_SDRAM_TOTAL_BANKS 1
239 #define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */
240 #define CFG_SDRAM_SPD_SIZE 0x100
241 #define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */
244 * Ethernet configuration
246 #define CONFIG_MPC8220_FEC 1
247 #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
248 #define CONFIG_PHY_ADDR 0x1F
251 * Miscellaneous configurable options
253 #define CFG_LONGHELP /* undef to save memory */
254 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
255 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
256 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
258 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
260 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
261 #define CFG_MAXARGS 16 /* max number of command args */
262 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
264 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
265 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
267 #define CFG_LOAD_ADDR 0x100000 /* default load address */
269 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
272 * Various low-level settings
274 #define CFG_HID0_INIT 0
275 #define CFG_HID0_FINAL 0
277 #endif /* __CONFIG_H */