3 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
31 #define CONFIG_MPC8220 1
32 #define CONFIG_SORCERY 1 /* Sorcery board */
34 #define CONFIG_SYS_TEXT_BASE 0xfff00000
36 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
38 /* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
39 determine the CPU speed. */
40 #define CONFIG_SYS_MPC8220_CLKIN 60000000 /* ... running at 60MHz */
41 #define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
44 * Serial console configuration
46 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC */
48 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
49 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
53 #define CONFIG_PCI_PNP 1
55 #define CONFIG_PCI_MEM_BUS 0x80000000
56 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
57 #define CONFIG_PCI_MEM_SIZE 0x10000000
59 #define CONFIG_PCI_IO_BUS 0x71000000
60 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
61 #define CONFIG_PCI_IO_SIZE 0x01000000
63 #define CONFIG_PCI_CFG_BUS 0x70000000
64 #define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS
65 #define CONFIG_PCI_CFG_SIZE 0x01000000
71 #define CONFIG_BOOTP_BOOTFILESIZE
72 #define CONFIG_BOOTP_BOOTPATH
73 #define CONFIG_BOOTP_GATEWAY
74 #define CONFIG_BOOTP_HOSTNAME
78 * Command line configuration.
80 #include <config_cmd_default.h>
82 #define CONFIG_CMD_BOOTD
83 #define CONFIG_CMD_CACHE
84 #define CONFIG_CMD_DHCP
85 #define CONFIG_CMD_DIAG
86 #define CONFIG_CMD_ELF
87 #define CONFIG_CMD_I2C
88 #define CONFIG_CMD_NET
89 #define CONFIG_CMD_NFS
90 #define CONFIG_CMD_PCI
91 #define CONFIG_CMD_PING
92 #define CONFIG_CMD_REGINFO
93 #define CONFIG_CMD_SDRAM
94 #define CONFIG_CMD_SNTP
100 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
101 #define CONFIG_HOSTNAME sorcery
103 #define CONFIG_PREBOOT "echo;" \
104 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
107 #undef CONFIG_BOOTARGS
109 #define CONFIG_EXTRA_ENV_SETTINGS \
111 "nfsargs=setenv bootargs root=/dev/nfs rw " \
112 "nfsroot=$serverip:$rootpath\0" \
113 "ramargs=setenv bootargs root=/dev/ram rw\0" \
114 "addip=setenv bootargs $bootargs " \
115 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
116 ":$hostname:$netdev:off panic=1\0" \
117 "flash_nfs=run nfsargs addip;" \
118 "bootm $kernel_addr\0" \
119 "flash_self=run ramargs addip;" \
120 "bootm $kernel_addr $ramdisk_addr\0" \
121 "net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \
122 "rootpath=/opt/eldk/ppc_82xx\0" \
123 "bootfile=/tftpboot/sorcery/uImage\0" \
124 "kernel_addr=FFE00000\0" \
125 "ramdisk_addr=FFB00000\0" \
127 #define CONFIG_BOOTCOMMAND "run flash_self"
129 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
131 #define CONFIG_EEPRO100
136 #define CONFIG_HARD_I2C 1
137 #define CONFIG_SYS_I2C_MODULE 1
138 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
139 #define CONFIG_SYS_I2C_SLAVE 0x7F
141 /* Use the HUSH parser */
142 #define CONFIG_SYS_HUSH_PARSER
145 * Flexbus Chipselect configuration
146 * Beware: Some CS# seem to be mandatory (if these CS# are not set,
147 * board can hang-up in unpredictable place).
148 * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
152 #define CONFIG_SYS_CS0_BASE 0xf800
153 #define CONFIG_SYS_CS0_MASK 0x08000000 /* 128 MB (two chips) */
154 #define CONFIG_SYS_CS0_CTRL 0x001019c0
157 #define CONFIG_SYS_CS1_BASE 0xf7e8
158 #define CONFIG_SYS_CS1_MASK 0x00040000 /* 256K */
159 #define CONFIG_SYS_CS1_CTRL 0x00101940 /* 8bit port size */
161 /* Atlas2 + Gemini */
162 #define CONFIG_SYS_CS2_BASE 0xf7e7
163 #define CONFIG_SYS_CS2_MASK 0x00010000 /* 64K*/
164 #define CONFIG_SYS_CS2_CTRL 0x001011c0 /* 16bit port size */
167 #define CONFIG_SYS_CS3_BASE 0xf7e6
168 #define CONFIG_SYS_CS3_MASK 0x00010000 /* 64K */
169 #define CONFIG_SYS_CS3_CTRL 0x00102140 /* 8Bit port size */
171 /* Foreign interface */
172 #define CONFIG_SYS_CS4_BASE 0xf7e5
173 #define CONFIG_SYS_CS4_MASK 0x00010000 /* 64K */
174 #define CONFIG_SYS_CS4_CTRL 0x00101dc0 /* 16bit port size */
177 #define CONFIG_SYS_CS5_BASE 0xf7e4
178 #define CONFIG_SYS_CS5_MASK 0x00010000 /* 64K */
179 #define CONFIG_SYS_CS5_CTRL 0x001000c0 /* 16bit port size */
181 #define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
182 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_FLASH0_BASE)
184 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
185 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
187 #define CONFIG_FLASH_CFI_DRIVER
188 #define CONFIG_SYS_FLASH_CFI
189 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
190 CONFIG_SYS_FLASH_BASE+0x04000000 } /* two banks */
193 * Environment settings
195 #define CONFIG_ENV_IS_IN_FLASH 1
196 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000000 - 0x40000)
197 #define CONFIG_ENV_SIZE 0x4000 /* 16K */
198 #define CONFIG_ENV_SECT_SIZE 0x20000
199 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + 0x20000)
200 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
202 #define CONFIG_ENV_OVERWRITE 1
204 #if defined CONFIG_ENV_IS_IN_FLASH
205 #undef CONFIG_ENV_IS_IN_NVRAM
206 #undef CONFIG_ENV_IS_IN_EEPROM
207 #elif defined CONFIG_ENV_IS_IN_NVRAM
208 #undef CONFIG_ENV_IS_IN_FLASH
209 #undef CONFIG_ENV_IS_IN_EEPROM
210 #elif defined CONFIG_ENV_IS_IN_EEPROM
211 #undef CONFIG_ENV_IS_IN_NVRAM
212 #undef CONFIG_ENV_IS_IN_FLASH
218 #define CONFIG_SYS_MBAR 0xF0000000
219 #define CONFIG_SYS_SDRAM_BASE 0x00000000
220 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
221 #define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
222 #define CONFIG_SYS_SRAM_SIZE 0x8000
224 /* Use SRAM until RAM will be available */
225 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
226 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in DPRAM */
228 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
229 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
232 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
233 # define CONFIG_SYS_RAMBOOT 1
236 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
237 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
238 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
240 /* SDRAM configuration (for SPD) */
241 #define CONFIG_SYS_SDRAM_TOTAL_BANKS 1
242 #define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */
243 #define CONFIG_SYS_SDRAM_SPD_SIZE 0x100
244 #define CONFIG_SYS_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */
246 /* SDRAM drive strength register (for SSTL_2 class II)*/
247 #define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
248 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
249 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
250 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
251 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))
254 * Ethernet configuration
256 #define CONFIG_MPC8220_FEC 1
257 #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
258 #define CONFIG_PHY_ADDR 0x1F
262 * Miscellaneous configurable options
264 #define CONFIG_SYS_LONGHELP /* undef to save memory */
265 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
266 #if defined(CONFIG_CMD_KGDB)
267 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
269 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
271 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
272 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
273 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
275 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
276 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
278 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
280 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
282 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
283 #if defined(CONFIG_CMD_KGDB)
284 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
288 * Various low-level settings
290 #define CONFIG_SYS_HID0_INIT 0
291 #define CONFIG_SYS_HID0_FINAL 0
294 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
295 #define CONFIG_SYS_HID0_FINAL HID0_ICE
298 #endif /* __CONFIG_H */