3 * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
5 * Configuation settings for the SPC1920 board.
7 * SPDX-License-Identifier: GPL-2.0+
13 #define CONFIG_SPC1920 1 /* SPC1920 board */
14 #define CONFIG_MPC885 1 /* MPC885 CPU */
16 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
18 #define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
19 #undef CONFIG_8xx_CONS_SMC2
20 #undef CONFIG_8xx_CONS_NONE
23 #define CONFIG_MII_INIT 1
24 #undef CONFIG_ETHER_ON_FEC1
25 #define CONFIG_ETHER_ON_FEC2
27 #define CONFIG_FEC2_PHY 1
29 #define CONFIG_BAUDRATE 19200
31 /* use PLD CLK4 instead of brg */
32 #define CONFIG_SYS_SPC1920_SMC1_CLK4
34 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
35 #define CONFIG_8xx_CPUCLK_DEFAULT 50000000
36 #define CONFIG_SYS_8xx_CPUCLK_MIN 40000000
37 #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
39 #define CONFIG_SYS_RESET_ADDRESS 0xC0000000
41 #define CONFIG_BOARD_EARLY_INIT_F
42 #define CONFIG_LAST_STAGE_INIT
45 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
50 #define CONFIG_ENV_OVERWRITE
52 #define CONFIG_NFSBOOTCOMMAND \
54 "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
55 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
58 #define CONFIG_BOOTCOMMAND \
59 "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
60 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
63 #undef CONFIG_BOOTARGS
65 #undef CONFIG_WATCHDOG /* watchdog disabled */
66 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
72 #define CONFIG_BOOTP_BOOTFILESIZE
73 #define CONFIG_BOOTP_BOOTPATH
74 #define CONFIG_BOOTP_GATEWAY
75 #define CONFIG_BOOTP_HOSTNAME
79 * Command line configuration.
81 #include <config_cmd_default.h>
83 #define CONFIG_CMD_ASKENV
84 #define CONFIG_CMD_DATE
85 #define CONFIG_CMD_ECHO
86 #define CONFIG_CMD_IMMAP
87 #define CONFIG_CMD_JFFS2
88 #define CONFIG_CMD_NET
89 #define CONFIG_CMD_PING
90 #define CONFIG_CMD_DHCP
91 #define CONFIG_CMD_I2C
92 #define CONFIG_CMD_MII
95 * Miscellaneous configurable options
97 #define CONFIG_SYS_LONGHELP /* undef to save memory */
98 #define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
99 #define CONFIG_SYS_HUSH_PARSER
101 #if defined(CONFIG_CMD_KGDB)
102 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
104 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
107 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
108 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
109 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
111 #define CONFIG_SYS_LOAD_ADDR 0x00100000
113 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
115 #define CONFIG_SYS_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 }
118 * Low Level Configuration Settings
119 * (address mappings, register initial values, etc.)
120 * You should know what you are doing if you make changes here.
123 /*-----------------------------------------------------------------------
124 * Internal Memory Mapped Register
126 #define CONFIG_SYS_IMMR 0xF0000000
128 /*-----------------------------------------------------------------------
129 * Definitions for initial stack pointer and data area (in DPRAM)
131 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
132 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
133 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
134 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
136 /*-----------------------------------------------------------------------
137 * Start addresses for the final memory configuration
138 * (Set up by the startup code)
139 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
141 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
142 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
145 * For booting Linux, the board info and command line data
146 * have to be in the first 8 MB of memory, since this is
147 * the maximum mapped by the Linux kernel during initialization.
149 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
151 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
152 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
155 #define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
157 #define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
158 #endif /* CONFIG_BZIP2 */
160 #define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */
165 /*-----------------------------------------------------------------------
168 #define CONFIG_SYS_FLASH_BASE 0xFE000000
169 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
170 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
171 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
172 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
174 /* Environment is in flash */
175 #define CONFIG_ENV_IS_IN_FLASH
176 #define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
177 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
179 #define CONFIG_ENV_OVERWRITE
181 /*-----------------------------------------------------------------------
182 * Cache Configuration
184 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
185 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
187 #ifdef CONFIG_CMD_DATE
188 # define CONFIG_RTC_DS3231
189 # define CONFIG_SYS_I2C_RTC_ADDR 0x68
192 /*-----------------------------------------------------------------------
195 #if defined(CONFIG_CMD_I2C)
196 /* enable I2C and select the hardware/software driver */
197 #undef CONFIG_HARD_I2C /* I2C with hardware support */
198 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
200 #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
201 #define CONFIG_SYS_I2C_SLAVE 0xFE
203 #ifdef CONFIG_SOFT_I2C
205 * Software (bit-bang) I2C driver configuration
207 #define PB_SCL 0x00000020 /* PB 26 */
208 #define PB_SDA 0x00000010 /* PB 27 */
210 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
211 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
212 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
213 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
214 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
215 else immr->im_cpm.cp_pbdat &= ~PB_SDA
216 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
217 else immr->im_cpm.cp_pbdat &= ~PB_SCL
218 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
219 #endif /* CONFIG_SOFT_I2C */
222 /*-----------------------------------------------------------------------
223 * SYPCR - System Protection Control 11-9
224 * SYPCR can only be written once after reset!
225 *-----------------------------------------------------------------------
226 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
228 #if defined(CONFIG_WATCHDOG)
229 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
230 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
232 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
235 /*-----------------------------------------------------------------------
236 * SIUMCR - SIU Module Configuration 11-6
237 *-----------------------------------------------------------------------
238 * PCMCIA config., multi-function pin tri-state
240 #define CONFIG_SYS_SIUMCR (SIUMCR_FRC)
242 /*-----------------------------------------------------------------------
243 * TBSCR - Time Base Status and Control 11-26
244 *-----------------------------------------------------------------------
245 * Clear Reference Interrupt Status, Timebase freezing enabled
247 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
249 /*-----------------------------------------------------------------------
250 * PISCR - Periodic Interrupt Status and Control 11-31
251 *-----------------------------------------------------------------------
252 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
254 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
256 /*-----------------------------------------------------------------------
257 * SCCR - System Clock and reset Control Register 15-27
258 *-----------------------------------------------------------------------
259 * Set clock output, timebase and RTC source and divider,
260 * power management and some other internal clocks
262 #define SCCR_MASK SCCR_EBDF11
263 /* #define CONFIG_SYS_SCCR SCCR_TBS */
264 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
265 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
268 /*-----------------------------------------------------------------------
269 * DER - Debug Enable Register
270 *-----------------------------------------------------------------------
271 * Set to zero to prevent the processor from entering debug mode
273 #define CONFIG_SYS_DER 0
276 /* Because of the way the 860 starts up and assigns CS0 the entire
277 * address space, we have to set the memory controller differently.
278 * Normally, you write the option register first, and then enable the
279 * chip select by writing the base register. For CS0, you must write
280 * the base register first, followed by the option register.
285 * Init Memory Controller:
288 /* BR0 and OR0 (FLASH) */
289 #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
292 /* used to re-map FLASH both when starting from SRAM or FLASH:
293 * restrict access enough to keep SRAM working (if any)
294 * but not too much to meddle with FLASH accesses
296 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
297 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
302 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
303 OR_SCY_6_CLK | OR_EHTR | OR_BI)
305 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
306 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
307 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
313 #define CONFIG_SYS_SDRAM_BASE 0x00000000
314 #define CONFIG_SYS_SDRAM_BASE_PRELIM CONFIG_SYS_SDRAM_BASE
315 #define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */
317 #define CONFIG_SYS_PRELIM_OR1_AM 0xF0000000
318 /* #define CONFIG_SYS_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */
319 #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
321 #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
322 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
324 /* #define CONFIG_SYS_OR1_FINAL ((CONFIG_SYS_OR1_AM & OR_AM_MSK) | CONFIG_SYS_OR1_TIMING) */
325 /* #define CONFIG_SYS_BR1_FINAL ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
327 #define CONFIG_SYS_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64))
328 #define CONFIG_SYS_PTA_PER_CLK 195
329 #define CONFIG_SYS_MBMR_PTB 195
330 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV16
331 #define CONFIG_SYS_MAR 0x88
333 #define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
339 MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
341 #define CONFIG_SYS_MBMR_9COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
347 MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
351 * DSP Host Port Interface CS3
353 #define CONFIG_SYS_SPC1920_HPI_BASE 0x90000000
354 #define CONFIG_SYS_PRELIM_OR3_AM 0xF8000000
356 #define CONFIG_SYS_OR3 (CONFIG_SYS_PRELIM_OR3_AM | \
361 #define CONFIG_SYS_BR3 ((CONFIG_SYS_SPC1920_HPI_BASE & BR_BA_MSK) | \
366 #define CONFIG_SYS_MAMR (MAMR_GPL_A4DIS | \
370 #define CONFIG_SPC1920_HPI_TEST
372 #ifdef CONFIG_SPC1920_HPI_TEST
373 #define HPI_REG(x) (*((volatile u16 *) (CONFIG_SYS_SPC1920_HPI_BASE + x)))
374 #define HPI_HPIC_1 HPI_REG(0)
375 #define HPI_HPIC_2 HPI_REG(2)
376 #define HPI_HPIA_1 HPI_REG(0x2000008)
377 #define HPI_HPIA_2 HPI_REG(0x2000008 + 2)
378 #define HPI_HPID_INC_1 HPI_REG(0x1000004)
379 #define HPI_HPID_INC_2 HPI_REG(0x1000004 + 2)
380 #define HPI_HPID_NOINC_1 HPI_REG(0x300000c)
381 #define HPI_HPID_NOINC_2 HPI_REG(0x300000c + 2)
382 #endif /* CONFIG_SPC1920_HPI_TEST */
385 * Ramtron FM18L08 FRAM 32KB on CS4
387 #define CONFIG_SYS_SPC1920_FRAM_BASE 0x80100000
388 #define CONFIG_SYS_PRELIM_OR4_AM 0xffff8000
389 #define CONFIG_SYS_OR4 (CONFIG_SYS_PRELIM_OR4_AM | \
395 #define CONFIG_SYS_BR4 ((CONFIG_SYS_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
400 #define CONFIG_SYS_SPC1920_PLD_BASE 0x80000000
401 #define CONFIG_SYS_PRELIM_OR5_AM 0xffff8000
403 #define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PRELIM_OR5_AM | \
410 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
412 #endif /* __CONFIG_H */