3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
6 * SPDX-License-Identifier: GPL-2.0+
13 * High Level Configuration Options
15 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_MPC83xx 1 /* MPC83xx family */
17 #define CONFIG_MPC830x 1 /* MPC830x family */
18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
19 #define CONFIG_STRIDER 1 /* STRIDER board specific */
21 #define CONFIG_SYS_TEXT_BASE 0xFE000000
23 #define CONFIG_BOARD_EARLY_INIT_R
24 #define CONFIG_LAST_STAGE_INIT
26 #define CONFIG_FSL_ESDHC
27 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
29 #define CONFIG_GENERIC_MMC
31 #define CONFIG_SYS_ALT_MEMTEST
33 #define CONFIG_CMD_FPGAD
34 #define CONFIG_CMD_IOLOOP
39 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
40 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
43 * Hardware Reset Configuration Word
44 * if CLKIN is 66.66MHz, then
45 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
46 * We choose the A type silicon as default, so the core is 400Mhz.
48 #define CONFIG_SYS_HRCW_LOW (\
49 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
50 HRCWL_DDR_TO_SCB_CLK_2X1 |\
52 HRCWL_CSB_TO_CLKIN_4X1 |\
53 HRCWL_CORE_TO_CSB_3X1)
55 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
56 * in 8308's HRCWH according to the manual, but original Freescale's
57 * code has them and I've expirienced some problems using the board
58 * with BDI3000 attached when I've tried to set these bits to zero
59 * (UART doesn't work after the 'reset run' command).
61 #define CONFIG_SYS_HRCW_HIGH (\
63 HRCWH_PCI1_ARBITER_ENABLE |\
65 HRCWH_FROM_0XFFF00100 |\
66 HRCWH_BOOTSEQ_DISABLE |\
67 HRCWH_SW_WATCHDOG_DISABLE |\
68 HRCWH_ROM_LOC_LOCAL_16BIT |\
69 HRCWH_RL_EXT_LEGACY |\
70 HRCWH_TSEC1M_IN_MII |\
71 HRCWH_TSEC2M_IN_RGMII |\
77 #define CONFIG_SYS_SICRH (\
83 SICRH_IEEE1588_A_GPIO |\
86 SICRH_IEEE1588_B_GPIO |\
91 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
92 #define CONFIG_SYS_SICRL (\
97 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
102 #define CONFIG_SYS_IMMR 0xE0000000
107 #define CONFIG_FSL_SERDES
108 #define CONFIG_FSL_SERDES1 0xe3000
113 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
114 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
115 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
120 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
121 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
122 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
123 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
124 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
131 * Manually set up DDR parameters
132 * consist of one chip NT5TU64M16HG from NANYA
135 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
137 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
138 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
139 | CSCONFIG_ODT_RD_NEVER \
140 | CSCONFIG_ODT_WR_ONLY_CURRENT \
141 | CSCONFIG_BANK_BIT_3 \
142 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
144 #define CONFIG_SYS_DDR_TIMING_3 0
145 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
146 | (0 << TIMING_CFG0_WRT_SHIFT) \
147 | (0 << TIMING_CFG0_RRT_SHIFT) \
148 | (0 << TIMING_CFG0_WWT_SHIFT) \
149 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
150 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
151 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
152 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
154 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
155 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
156 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
157 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
158 | (9 << TIMING_CFG1_REFREC_SHIFT) \
159 | (2 << TIMING_CFG1_WRREC_SHIFT) \
160 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
161 | (2 << TIMING_CFG1_WRTORD_SHIFT))
163 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
164 | (4 << TIMING_CFG2_CPO_SHIFT) \
165 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
166 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
167 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
168 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
169 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
171 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
172 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
174 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
175 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
179 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
180 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
181 | (0x0242 << SDRAM_MODE_SD_SHIFT))
182 /* ODT 150ohm CL=4, AL=0 on SDRAM */
183 #define CONFIG_SYS_DDR_MODE2 0x00000000
188 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
189 #define CONFIG_SYS_MEMTEST_END 0x07f00000
192 * The reserved memory
194 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
196 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
197 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
200 * Initial RAM Base Address Setup
202 #define CONFIG_SYS_INIT_RAM_LOCK 1
203 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
204 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
205 #define CONFIG_SYS_GBL_DATA_OFFSET \
206 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
209 * Local Bus Configuration & Clock Setup
211 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
212 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
213 #define CONFIG_SYS_LBC_LBCR 0x00040000
216 * FLASH on the Local Bus
218 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
219 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
220 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
221 #define CONFIG_FLASH_CFI_LEGACY
222 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
224 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
225 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
226 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
228 /* Window base at flash base */
229 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
230 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
232 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
233 | BR_PS_16 /* 16 bit port */ \
234 | BR_MS_GPCM /* MSEL = GPCM */ \
236 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
245 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
246 #define CONFIG_SYS_MAX_FLASH_SECT 135
248 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
249 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
254 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
255 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
257 /* Window base at FPGA base */
258 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
259 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
261 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
262 | BR_PS_16 /* 16 bit port */ \
263 | BR_MS_GPCM /* MSEL = GPCM */ \
266 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
270 | OR_GPCM_TRLX_CLEAR \
271 | OR_GPCM_EHTR_CLEAR)
273 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
274 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
276 #define CONFIG_SYS_FPGA_COUNT 1
278 #define CONFIG_SYS_MCLINK_MAX 3
280 #define CONFIG_SYS_FPGA_PTR \
281 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
283 #define CONFIG_SYS_FPGA_NO_RFL_HI
288 #define CONFIG_CONS_INDEX 2
289 #define CONFIG_SYS_NS16550_SERIAL
290 #define CONFIG_SYS_NS16550_REG_SIZE 1
291 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
293 #define CONFIG_SYS_BAUDRATE_TABLE \
294 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
296 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
297 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
299 /* Pass open firmware flat tree */
302 #define CONFIG_SYS_I2C
303 #define CONFIG_SYS_I2C_FSL
304 #define CONFIG_SYS_FSL_I2C_SPEED 400000
305 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
306 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
308 #define CONFIG_PCA953X /* NXP PCA9554 */
309 #define CONFIG_CMD_PCA953X
310 #define CONFIG_CMD_PCA953X_INFO
311 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
312 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
314 #define CONFIG_PCA9698 /* NXP PCA9698 */
316 #define CONFIG_SYS_I2C_IHS
317 #define CONFIG_SYS_I2C_IHS_CH0
318 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
319 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
320 #define CONFIG_SYS_I2C_IHS_CH1
321 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
322 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
323 #define CONFIG_SYS_I2C_IHS_CH2
324 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
325 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
326 #define CONFIG_SYS_I2C_IHS_CH3
327 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
328 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
330 #ifdef CONFIG_STRIDER_CON_DP
331 #define CONFIG_SYS_I2C_IHS_DUAL
332 #define CONFIG_SYS_I2C_IHS_CH0_1
333 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
334 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
335 #define CONFIG_SYS_I2C_IHS_CH1_1
336 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
337 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
338 #define CONFIG_SYS_I2C_IHS_CH2_1
339 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
340 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
341 #define CONFIG_SYS_I2C_IHS_CH3_1
342 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
343 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
347 * Software (bit-bang) I2C driver configuration
349 #define CONFIG_SYS_I2C_SOFT
350 #define CONFIG_SOFT_I2C_READ_REPEATED_START
351 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
352 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
353 #define I2C_SOFT_DECLARATIONS2
354 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
355 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
356 #define I2C_SOFT_DECLARATIONS3
357 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
358 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
359 #define I2C_SOFT_DECLARATIONS4
360 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
361 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
362 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
363 #define I2C_SOFT_DECLARATIONS5
364 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
365 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
366 #define I2C_SOFT_DECLARATIONS6
367 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
368 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
369 #define I2C_SOFT_DECLARATIONS7
370 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
371 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
372 #define I2C_SOFT_DECLARATIONS8
373 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
374 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
376 #ifdef CONFIG_STRIDER_CON_DP
377 #define I2C_SOFT_DECLARATIONS9
378 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
379 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
380 #define I2C_SOFT_DECLARATIONS10
381 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
382 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
383 #define I2C_SOFT_DECLARATIONS11
384 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
385 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
386 #define I2C_SOFT_DECLARATIONS12
387 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
388 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
391 #ifdef CONFIG_STRIDER_CON
392 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
393 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
394 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
395 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
396 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
398 #elif defined(CONFIG_STRIDER_CON_DP)
399 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
400 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7}
401 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7}
402 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
403 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
405 #elif defined(CONFIG_STRIDER_CPU_DP)
406 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
407 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
408 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
409 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
412 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
413 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
414 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
415 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
420 void fpga_gpio_set(unsigned int bus, int pin);
421 void fpga_gpio_clear(unsigned int bus, int pin);
422 int fpga_gpio_get(unsigned int bus, int pin);
423 void fpga_control_set(unsigned int bus, int pin);
424 void fpga_control_clear(unsigned int bus, int pin);
427 #ifdef CONFIG_STRIDER_CON
428 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
429 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
430 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
431 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
432 #elif defined(CONFIG_STRIDER_CON_DP)
433 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
434 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
435 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
437 #define I2C_SDA_GPIO 0x0040
438 #define I2C_SCL_GPIO 0x0020
439 #define I2C_FPGA_IDX I2C_ADAP_HWNR
442 #ifdef CONFIG_STRIDER_CON_DP
445 if (I2C_ADAP_HWNR > 7) \
446 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
448 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
451 #define I2C_ACTIVE { }
454 #define I2C_TRISTATE { }
456 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
457 #define I2C_SDA(bit) \
460 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
462 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
464 #define I2C_SCL(bit) \
467 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
469 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
471 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
474 * Software (bit-bang) MII driver configuration
476 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
477 #define CONFIG_BITBANGMII_MULTI
482 #define CONFIG_SYS_OSD_SCREENS 1
483 #define CONFIG_SYS_DP501_DIFFERENTIAL
484 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
486 #ifdef CONFIG_STRIDER_CON_DP
487 #define CONFIG_SYS_OSD_DH
492 * Addresses are mapped 1-1.
494 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
495 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
496 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
497 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
498 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
499 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
500 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
501 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
502 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
504 /* enable PCIE clock */
505 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
507 #define CONFIG_PCI_INDIRECT_BRIDGE
510 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
511 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
516 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
517 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
518 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
521 * TSEC ethernet configuration
523 #define CONFIG_MII 1 /* MII PHY management */
525 #define CONFIG_TSEC1_NAME "eTSEC0"
526 #define TSEC1_PHY_ADDR 1
527 #define TSEC1_PHYIDX 0
528 #define TSEC1_FLAGS 0
530 /* Options are: eTSEC[0-1] */
531 #define CONFIG_ETHPRIME "eTSEC0"
537 #define CONFIG_ENV_IS_IN_FLASH 1
538 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
539 CONFIG_SYS_MONITOR_LEN)
540 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
541 #define CONFIG_ENV_SIZE 0x2000
542 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
543 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
545 #define CONFIG_ENV_IS_NOWHERE
546 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
549 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
550 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
553 * Command line configuration.
555 #define CONFIG_CMD_PCI
557 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
558 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
561 * Miscellaneous configurable options
563 #define CONFIG_SYS_LONGHELP /* undef to save memory */
564 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
565 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
567 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
569 /* Print Buffer Size */
570 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
571 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
572 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
575 * For booting Linux, the board info and command line data
576 * have to be in the first 256 MB of memory, since this is
577 * the maximum mapped by the Linux kernel during initialization.
579 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
584 #define CONFIG_SYS_HID0_INIT 0x000000000
585 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
586 HID0_ENABLE_INSTRUCTION_CACHE | \
587 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
588 #define CONFIG_SYS_HID2 HID2_HBE
594 /* DDR: cache cacheable */
595 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
597 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
599 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
600 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
602 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
603 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
604 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
605 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
607 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
608 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
610 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
611 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
613 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
615 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
616 BATL_CACHEINHIBIT | \
618 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
620 /* Stack in dcache: cacheable, no memory coherence */
621 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
622 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
624 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
625 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
628 * Environment Configuration
631 #define CONFIG_ENV_OVERWRITE
633 #if defined(CONFIG_TSEC_ENET)
634 #define CONFIG_HAS_ETH0
637 #define CONFIG_BAUDRATE 115200
639 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
642 #define CONFIG_HOSTNAME hrcon
643 #define CONFIG_ROOTPATH "/opt/nfsroot"
644 #define CONFIG_BOOTFILE "uImage"
646 #define CONFIG_PREBOOT /* enable preboot variable */
648 #define CONFIG_EXTRA_ENV_SETTINGS \
650 "consoledev=ttyS1\0" \
651 "u-boot=u-boot.bin\0" \
652 "kernel_addr=1000000\0" \
653 "fdt_addr=C00000\0" \
654 "fdtfile=hrcon.dtb\0" \
655 "load=tftp ${loadaddr} ${u-boot}\0" \
656 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
657 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
658 " +${filesize};cp.b ${fileaddr} " \
659 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
660 "upd=run load update\0" \
662 #define CONFIG_NFSBOOTCOMMAND \
663 "setenv bootargs root=/dev/nfs rw " \
664 "nfsroot=$serverip:$rootpath " \
665 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
666 "console=$consoledev,$baudrate $othbootargs;" \
667 "tftp ${kernel_addr} $bootfile;" \
668 "tftp ${fdt_addr} $fdtfile;" \
669 "bootm ${kernel_addr} - ${fdt_addr}"
671 #define CONFIG_MMCBOOTCOMMAND \
672 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
673 "console=$consoledev,$baudrate $othbootargs;" \
674 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
675 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
676 "bootm ${kernel_addr} - ${fdt_addr}"
678 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
680 #endif /* __CONFIG_H */