2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2005-2007
6 * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #define CONFIG_405EP 1 /* this is a PPC405 CPU */
32 #define CONFIG_4xx 1 /* member of PPC4xx family */
33 #define CONFIG_TAIHU 1 /* on a taihu board */
35 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
37 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
39 #define CONFIG_NO_SERIAL_EEPROM
41 /*----------------------------------------------------------------------------*/
42 #ifdef CONFIG_NO_SERIAL_EEPROM
45 !-------------------------------------------------------------------------------
46 ! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
47 ! assuming a 33MHz input clock to the 405EP from the C9531.
48 !-------------------------------------------------------------------------------
50 #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
51 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
52 PLL_MALDIV_1 | PLL_PCIDIV_3)
53 #define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
54 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
55 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
56 #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
57 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
58 PLL_MALDIV_1 | PLL_PCIDIV_1)
59 #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
60 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
61 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
63 #define PLLMR0_DEFAULT PLLMR0_333_111_55_37
64 #define PLLMR1_DEFAULT PLLMR1_333_111_55_37
65 #define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
66 #define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
69 /*----------------------------------------------------------------------------*/
71 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
73 #define CONFIG_ENV_OVERWRITE 1
74 #define CONFIG_PREBOOT "echo;" \
75 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
78 #undef CONFIG_BOOTARGS
79 #define CONFIG_EXTRA_ENV_SETTINGS \
80 "bootfile=/tftpboot/taihu/uImage\0" \
81 "rootpath=/opt/eldk/ppc_4xx\0" \
83 "nfsargs=setenv bootargs root=/dev/nfs rw " \
84 "nfsroot=${serverip}:${rootpath}\0" \
85 "ramargs=setenv bootargs root=/dev/ram rw\0" \
86 "addip=setenv bootargs ${bootargs} " \
87 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
88 ":${hostname}:${netdev}:off panic=1\0" \
89 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
90 "flash_nfs=run nfsargs addip addtty;" \
91 "bootm ${kernel_addr}\0" \
92 "flash_self=run ramargs addip addtty;" \
93 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
94 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
96 "kernel_addr=FC000000\0" \
97 "ramdisk_addr=FC180000\0" \
98 "load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \
99 "update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \
100 "cp.b 200000 FFFC0000 40000\0" \
101 "upd=run load;run update\0" \
103 #define CONFIG_BOOTCOMMAND "run flash_self"
106 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
108 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
111 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
112 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
114 #define CONFIG_MII 1 /* MII PHY management */
115 #define CONFIG_PHY_ADDR 0x14 /* PHY address */
116 #define CONFIG_HAS_ETH1
117 #define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
118 #define CONFIG_NET_MULTI 1
119 #define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
120 #define CONFIG_PHY_RESET 1
122 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
138 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
139 #include <cmd_confdefs.h>
141 #undef CONFIG_WATCHDOG /* watchdog disabled */
143 #undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
144 #define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
145 #define CFG_SDRAM_BANKS 2
148 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
150 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
151 #define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
153 /* SDRAM timings used in datasheet */
154 #define CFG_SDRAM_CL 3 /* CAS latency */
155 #define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
156 #define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
157 #define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
158 #define CFG_SDRAM_tRFC 66 /* Auto refresh period */
161 * Miscellaneous configurable options
163 #define CFG_LONGHELP /* undef to save memory */
164 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
165 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
166 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
168 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
170 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */
171 #define CFG_MAXARGS 16 /* max number of command args */
172 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
174 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
175 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
178 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
179 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
180 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
181 * The Linux BASE_BAUD define should match this configuration.
182 * baseBaud = cpuClock/(uartDivisor*16)
183 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
184 * set Linux BASE_BAUD to 403200.
186 #undef CONFIG_SERIAL_SOFTWARE_FIFO
187 #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
188 #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
189 #define CFG_BASE_BAUD 691200
191 #define CONFIG_BAUDRATE 115200
193 #define CONFIG_UART1_CONSOLE 1
196 /* The following table includes the supported baudrates */
197 #define CFG_BAUDRATE_TABLE \
198 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
200 #define CFG_LOAD_ADDR 0x100000 /* default load address */
201 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
203 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
205 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
206 #define CONFIG_LOOPW 1 /* enable loopw command */
207 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
208 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
210 /*-----------------------------------------------------------------------
212 *-----------------------------------------------------------------------
214 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
215 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
216 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
217 #define CFG_I2C_SLAVE 0x7F
219 #define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
220 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
222 #if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
223 #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
224 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
228 #define CONFIG_SOFT_SPI
229 #define SPI_SCL spi_scl
230 #define SPI_SDA spi_sda
231 #define SPI_READ spi_read()
232 #define SPI_DELAY udelay(2)
236 unsigned char spi_read(void);
239 /* standard dtt sensor configuration */
240 #define CONFIG_DTT_DS1775 1
241 #define CONFIG_DTT_SENSORS { 0 }
243 /*-----------------------------------------------------------------------
245 *-----------------------------------------------------------------------
247 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
248 #define PCI_HOST_FORCE 1 /* configure as pci host */
249 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
251 #define CONFIG_PCI /* include pci support */
252 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
253 #define CONFIG_PCI_PNP /* do pci plug-and-play */
254 /* resource configuration */
255 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
257 #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
258 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
259 #define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
260 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
261 #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
262 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
263 #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
264 #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
265 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
266 #define CONFIG_EEPRO100 1
268 /*-----------------------------------------------------------------------
269 * Start addresses for the final memory configuration
270 * (Set up by the startup code)
271 * Please note that CFG_SDRAM_BASE _must_ start at 0
273 #define CFG_SDRAM_BASE 0x00000000
274 #define CFG_FLASH_BASE 0xFFE00000
275 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
276 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
277 #define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
280 * For booting Linux, the board info and command line data
281 * have to be in the first 8 MB of memory, since this is
282 * the maximum mapped by the Linux kernel during initialization.
284 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
286 /*-----------------------------------------------------------------------
290 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
291 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
293 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
294 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
296 #define CFG_FLASH_ADDR0 0x555
297 #define CFG_FLASH_ADDR1 0x2aa
298 #define CFG_FLASH_WORD_SIZE unsigned short
300 #ifdef CFG_ENV_IS_IN_FLASH
301 #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
302 #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
303 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
305 /* Address and size of Redundant Environment Sector */
306 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
307 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
308 #endif /* CFG_ENV_IS_IN_FLASH */
310 /*-----------------------------------------------------------------------
313 #define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
314 #define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
316 #ifdef CFG_ENV_IS_IN_NVRAM
317 #define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
318 #define CFG_ENV_ADDR \
319 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env*/
322 /*-----------------------------------------------------------------------
323 * PPC405 GPIO Configuration
325 #define CFG_440_GPIO_TABLE { /* GPIO Alternate1 */ \
328 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
329 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
330 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
331 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
332 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
333 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
334 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
335 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
336 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
337 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
338 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
339 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
340 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
341 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
342 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
343 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
344 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
345 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
346 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
347 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
348 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
349 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
350 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
351 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
352 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
353 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
354 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
355 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
356 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
357 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
358 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
359 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
363 /*-----------------------------------------------------------------------
364 * Cache Configuration
366 #define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
367 #define CFG_CACHELINE_SIZE 32
368 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
369 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
373 * Init Memory Controller:
375 * BR0/1 and OR0/1 (FLASH)
378 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
379 #define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */
381 /*-----------------------------------------------------------------------
382 * Definitions for initial stack pointer and data area (in data cache)
384 /* use on chip memory (OCM) for temperary stack until sdram is tested */
385 #define CFG_TEMP_STACK_OCM 1
387 /* On Chip Memory location */
388 #define CFG_OCM_DATA_ADDR 0xF8000000
389 #define CFG_OCM_DATA_SIZE 0x1000
390 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
391 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
393 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
394 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
395 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
397 /*-----------------------------------------------------------------------
398 * External Bus Controller (EBC) Setup
401 /* Memory Bank 0 (Flash/SRAM) initialization */
402 #define CFG_EBC_PB0AP 0x03815600
403 #define CFG_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
405 /* Memory Bank 1 (NVRAM/RTC) initialization */
406 #define CFG_EBC_PB1AP 0x05815600
407 #define CFG_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
409 /* Memory Bank 2 (USB device) initialization */
410 #define CFG_EBC_PB2AP 0x03016600
411 #define CFG_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
413 /* Memory Bank 3 (LCM and D-flip-flop) initialization */
414 #define CFG_EBC_PB3AP 0x158FF600
415 #define CFG_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
417 /* Memory Bank 4 (not install) initialization */
418 #define CFG_EBC_PB4AP 0x158FF600
419 #define CFG_EBC_PB4CR 0x5021A000
421 /*-----------------------------------------------------------------------
422 * Definitions for GPIO setup (PPC405EP specific)
424 * GPIO0[0] - External Bus Controller BLAST output
425 * GPIO0[1-9] - Instruction trace outputs
426 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
427 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
428 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
429 * GPIO0[24-27] - UART0 control signal inputs/outputs
430 * GPIO0[28-29] - UART1 data signal input/output
431 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
433 #define CFG_GPIO0_OSRH 0x15555550 /* output select high/low */
434 #define CFG_GPIO0_OSRL 0x00000110
435 #define CFG_GPIO0_ISR1H 0x00000001 /* input select high/low */
436 #define CFG_GPIO0_ISR1L 0x15545440
437 #define CFG_GPIO0_TSRH 0x00000000 /* three-state select high/low */
438 #define CFG_GPIO0_TSRL 0x00000000
439 #define CFG_GPIO0_TCR 0xFFFE8117 /* three-state control */
440 #define CFG_GPIO0_ODR 0x00000000 /* open drain */
442 #define GPIO0 0 /* GPIO controller 0 */
444 /* the GPIO macros in include/ppc405.h for High/Low registers are backwards */
446 #define GPIOx_OSL (GPIO0_OSRH-GPIO_BASE)
447 #define GPIOx_TSL (GPIO0_TSRH-GPIO_BASE)
448 #define GPIOx_IS1L (GPIO0_ISR1H-GPIO_BASE)
449 #define GPIOx_IS2L (GPIO0_ISR1H-GPIO_BASE)
450 #define GPIOx_IS3L (GPIO0_ISR1H-GPIO_BASE)
452 #define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO output select */
453 #define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO three-state select */
454 #define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO input select */
455 #define GPIO_IS2(x) (x+GPIOx_IS1L)
456 #define GPIO_IS3(x) (x+GPIOx_IS1L)
458 #define CPLD_REG0_ADDR 0x50100000
459 #define CPLD_REG1_ADDR 0x50100001
461 * Internal Definitions
465 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
466 #define BOOTFLAG_WARM 0x02 /* Software reboot */
468 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
469 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
470 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
473 #endif /* __CONFIG_H */