3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * Copyright (C) 2009 TechNexion Ltd.
7 * SPDX-License-Identifier: GPL-2.0+
14 * High Level Configuration Options
16 #define CONFIG_OMAP /* in a TI OMAP core */
17 #define CONFIG_OMAP_GPIO
18 #define CONFIG_OMAP_COMMON
19 /* Common ARM Erratas */
20 #define CONFIG_ARM_ERRATA_454179
21 #define CONFIG_ARM_ERRATA_430973
22 #define CONFIG_ARM_ERRATA_621766
24 #define CONFIG_SYS_TEXT_BASE 0x80008000
26 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
28 #include <asm/arch/cpu.h> /* get chip and board defs */
29 #include <asm/arch/omap.h>
32 #define V_OSCK 26000000 /* Clock output from T2 */
33 #define V_SCLK (V_OSCK >> 1)
35 #define CONFIG_MISC_INIT_R
37 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
38 #define CONFIG_SETUP_MEMORY_TAGS
39 #define CONFIG_INITRD_TAG
40 #define CONFIG_REVISION_TAG
43 * Size of malloc() pool
45 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
46 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
51 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */
52 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
59 * NS16550 Configuration
61 #define CONFIG_SYS_NS16550_SERIAL
62 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
63 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
66 * select serial console configuration
68 #define CONFIG_CONS_INDEX 1
69 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
70 #define CONFIG_SERIAL1 /* UART1 */
72 /* allow to overwrite serial and ethaddr */
73 #define CONFIG_ENV_OVERWRITE
74 #define CONFIG_BAUDRATE 115200
75 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
78 #define CONFIG_OMAP_HSMMC
79 #define CONFIG_GENERIC_MMC
80 #define CONFIG_DOS_PARTITION
83 #define CONFIG_OMAP3_GPIO_5
84 #define CONFIG_USB_EHCI
85 #define CONFIG_USB_EHCI_OMAP
86 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
87 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
89 /* commands to include */
90 #define CONFIG_CMD_NAND /* NAND support */
91 #define CONFIG_CMD_EEPROM
93 #define CONFIG_SYS_NO_FLASH
94 #define CONFIG_SYS_I2C
95 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000
96 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
97 #define CONFIG_SYS_I2C_OMAP34XX
98 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
99 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
100 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
105 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
109 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
112 #define CONFIG_AUTO_COMPLETE
115 * Miscellaneous configurable options
117 #define CONFIG_SYS_LONGHELP /* undef to save memory */
118 #define CONFIG_CMDLINE_EDITING
119 #define CONFIG_AUTO_COMPLETE
120 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
122 /* Print Buffer Size */
123 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
124 sizeof(CONFIG_SYS_PROMPT) + 16)
125 #define CONFIG_SYS_MAXARGS 32 /* max number of command */
127 /* Boot Argument Buffer Size */
128 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
129 /* memtest works on */
130 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
131 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
132 0x01F00000) /* 31MB */
134 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
138 * AM3517 has 12 GP timers, they can be driven by the system clock
139 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
140 * This rate is divided by a local divisor.
142 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
143 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
146 * Physical Memory Map
148 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
149 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
150 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
153 * FLASH and environment organization
156 /* **** PISMO SUPPORT *** */
158 #define CONFIG_NAND_OMAP_GPMC
159 #define CONFIG_ENV_IS_IN_NAND
160 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
162 /* Redundant Environment */
163 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
164 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
165 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
166 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
167 2 * CONFIG_SYS_ENV_SECT_SIZE)
168 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
170 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
171 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
172 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
173 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
174 CONFIG_SYS_INIT_RAM_SIZE - \
175 GENERATED_GBL_DATA_SIZE)
178 * ethernet support, EMAC
181 #define CONFIG_DRIVER_TI_EMAC
182 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
184 #define CONFIG_EMAC_MDIO_PHY_NUM 0
185 #define CONFIG_BOOTP_DNS
186 #define CONFIG_BOOTP_DNS2
187 #define CONFIG_BOOTP_SEND_HOSTNAME
188 #define CONFIG_NET_RETRY_COUNT 10
190 /* Defines for SPL */
191 #define CONFIG_SPL_FRAMEWORK
192 #define CONFIG_SPL_BOARD_INIT
193 #define CONFIG_SPL_CONSOLE
194 #define CONFIG_SPL_NAND_SIMPLE
195 #define CONFIG_SPL_NAND_SOFTECC
196 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
198 #define CONFIG_SPL_NAND_BASE
199 #define CONFIG_SPL_NAND_DRIVERS
200 #define CONFIG_SPL_NAND_ECC
201 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
203 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
204 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
205 CONFIG_SPL_TEXT_BASE)
206 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
208 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
209 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
210 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
211 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
213 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
214 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
215 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
218 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
219 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
221 /* RAW SD card / eMMC */
222 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
223 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
224 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
226 /* NAND boot config */
227 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
228 #define CONFIG_SYS_NAND_PAGE_COUNT 64
229 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
230 #define CONFIG_SYS_NAND_OOBSIZE 64
231 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
232 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
233 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
234 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
235 48, 49, 50, 51, 52, 53, 54, 55,\
236 56, 57, 58, 59, 60, 61, 62, 63}
237 #define CONFIG_SYS_NAND_ECCSIZE 256
238 #define CONFIG_SYS_NAND_ECCBYTES 3
239 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
240 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
242 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
244 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
245 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
247 #define CONFIG_CMD_UBIFS
248 #define CONFIG_RBTREE
250 #define CONFIG_MTD_PARTITIONS
251 #define CONFIG_MTD_DEVICE
252 #define CONFIG_CMD_MTDPARTS
254 /* Setup MTD for NAND on the SOM */
255 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
256 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
257 "1m(u-boot),256k(env1)," \
258 "256k(env2),6m(kernel),-(rootfs)"
260 #define CONFIG_TAM3517_SETTINGS \
262 "nandargs=setenv bootargs root=${nandroot} " \
263 "rootfstype=${nandrootfstype}\0" \
264 "nfsargs=setenv bootargs root=/dev/nfs rw " \
265 "nfsroot=${serverip}:${rootpath}\0" \
266 "ramargs=setenv bootargs root=/dev/ram rw\0" \
267 "addip_sta=setenv bootargs ${bootargs} " \
268 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
269 ":${hostname}:${netdev}:off panic=1\0" \
270 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
271 "addip=if test -n ${ipdyn};then run addip_dyn;" \
272 "else run addip_sta;fi\0" \
273 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
274 "addtty=setenv bootargs ${bootargs}" \
275 " console=ttyO0,${baudrate}\0" \
276 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
277 "loadaddr=82000000\0" \
278 "kernel_addr_r=82000000\0" \
279 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
280 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
281 "flash_self=run ramargs addip addtty addmtd addmisc;" \
282 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
283 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
284 "bootm ${kernel_addr}\0" \
285 "nandboot=run nandargs addip addtty addmtd addmisc;" \
286 "nand read ${kernel_addr_r} kernel\0" \
287 "bootm ${kernel_addr_r}\0" \
288 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
289 "run nfsargs addip addtty addmtd addmisc;" \
290 "bootm ${kernel_addr_r}\0" \
291 "net_self=if run net_self_load;then " \
292 "run ramargs addip addtty addmtd addmisc;" \
293 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
294 "else echo Images not loades;fi\0" \
295 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
296 "load=tftp ${loadaddr} ${u-boot}\0" \
297 "loadmlo=tftp ${loadaddr} ${mlo}\0" \
298 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
299 "uboot_addr=0x80000\0" \
300 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
301 "nand write ${loadaddr} ${uboot_addr} 80000\0" \
302 "updatemlo=nandecc hw;nand erase 0 20000;" \
303 "nand write ${loadaddr} 0 20000\0" \
304 "upd=if run load;then echo Updating u-boot;if run update;" \
305 "then echo U-Boot updated;" \
306 "else echo Error updating u-boot !;" \
307 "echo Board without bootloader !!;" \
309 "else echo U-Boot not downloaded..exiting;fi\0" \
312 * this is common code for all TAM3517 boards.
313 * MAC address is stored from manufacturer in
316 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
318 * The I2C EEPROM on the TAM3517 contains
319 * mac address and production data
321 struct tam3517_module_info {
326 * bit 0~47 : sequence number
327 * bit 48~55 : week of year, from 0.
330 unsigned long long sequence_number;
333 * bit 0~7 : revision fixed
334 * bit 8~15 : revision major
337 unsigned int revision;
338 unsigned char eth_addr[4][8];
339 unsigned char _rev[100];
342 #define TAM3517_READ_EEPROM(info, ret) \
344 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
345 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
346 (void *)info, sizeof(*info))) \
352 #define TAM3517_READ_MAC_FROM_EEPROM(info) \
354 char buf[80], ethname[20]; \
356 memset(buf, 0, sizeof(buf)); \
357 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
358 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
359 (info)->eth_addr[i][5], \
360 (info)->eth_addr[i][4], \
361 (info)->eth_addr[i][3], \
362 (info)->eth_addr[i][2], \
363 (info)->eth_addr[i][1], \
364 (info)->eth_addr[i][0]); \
367 sprintf(ethname, "eth%daddr", i); \
369 strcpy(ethname, "ethaddr"); \
370 printf("Setting %s from EEPROM with %s\n", ethname, buf);\
371 setenv(ethname, buf); \
375 /* The following macros are taken from Technexion's documentation */
376 #define TAM3517_sequence_number(info) \
377 ((info)->sequence_number % 0x1000000000000LL)
378 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
379 #define TAM3517_year(info) ((info)->sequence_number >> 56)
380 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
381 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
382 #define TAM3517_revision_tn(info) ((info)->revision >> 16)
384 #define TAM3517_PRINT_SOM_INFO(info) \
386 printf("Vendor:%s\n", (info)->customer); \
387 printf("SOM: %s\n", (info)->product); \
388 printf("SeqNr: %02llu%02llu%012llu\n", \
389 TAM3517_year(info), \
390 TAM3517_week_of_year(info), \
391 TAM3517_sequence_number(info)); \
392 printf("Rev: TN%u %u.%u\n", \
393 TAM3517_revision_tn(info), \
394 TAM3517_revision_major(info), \
395 TAM3517_revision_fixed(info)); \
400 #endif /* __TAM3517_H */